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AD9699 Datasheet(PDF) 1 Page - Analog Devices |
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AD9699 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 121 page ![]() Data Sheet AD9699 14-Bit, 3 GSPS, JESD204B, Single Analog-to-Digital Converter Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. FEATURES ► JESD204B (Subclass 1) coded serial digital outputs ► Support for lane rates up to 16 Gbps per lane ► 2 W total power at 3 GSPS (default settings) ► Performance at −2 dBFS amplitude, 2.6 GHz input ► SFDR = 70 dBFS ► SNR = 57.2 dBFS ► Performance at −9 dBFS amplitude, 2.6 GHz input ► SFDR = 78 dBFS ► SNR = 59.5 dBFS ► Integrated input buffer ► Noise density = −152 dBFS/Hz ► 0.975 V, 1.9 V, and 2.5 V dc supply operation ► 9 GHz analog input full power bandwidth (−3 dB) ► Amplitude detect bits for efficient AGC implementation ► 4 integrated digital downconverters ► 48-bit NCO ► 4 cascaded half-band filters ► Phase coherent NCO switching ► Up to 4 channels available ► Serial port control ► Integer clock with divide by 2 and divide by 4 options ► Flexible JESD204B lane configurations ► On-chip dither APPLICATIONS ► Diversity multiband and multimode digital receivers ► 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A ► Electronic test and measurement systems ► Phased array radar and electronic warfare ► DOCSIS 3.0 CMTS upstream receive paths ► HFC digital reverse path receivers ► LIDAR FUNCTIONAL BLOCK DIAGRAM Figure 1. |
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