AD9699 datasheet(23/121 Pages) AD

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Data Sheet

AD9699

THEORY OF OPERATION

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Rev. 0 | 23 of 121

Input Common Mode

The analog input of the AD9699 is internally biased to the common-

mode voltage, as shown in Figure 57. The common-mode buffer

has a limited range in that the performance suffers greatly if the

common-mode voltage drops by more than 50 mV on either side of

the nominal value.

For dc-coupled applications, the recommended operation proce-

dure is to export the common-mode voltage to the VREF pin using

the SPI writes listed in this section. The common-mode voltage

must be set by the exported value to ensure proper ADC operation.

Disconnect the internal common-mode buffer from the analog input

using Register 0x1908.

When performing SPI writes for dc coupling operation, use the

following register settings in order:

1. Set Register 0x1908, Bit 2 to disconnect the internal common-

mode buffer from the analog input. Note that this is a local

2. Set Register 0x18A6 to 0x00 to turn off the voltage reference.

3. Set Register 0x18E6 to 0x00 to turn off the temperature diode

export.

4. Set Register 0x18E0 to 0x02.

5. Set Register 0x18E1 to 0x9A.

6. Set Register 0x18E2 to 0x1E.

7. Set Register 0x18E3, Bit 6 to 1 to turn on the VCM export.

8. Set Register 0x18E3, Bits[5:0] to the buffer current setting (Reg-

ister 0x1A4C and Register 0x1A4D) to improve the accuracy of

the common-mode export.

Figure 56 shows the block diagram representation of a dc-coupled

application.

Figure 56. DC-Coupled Application Using the AD9699

Analog Input Buffer Controls and SFDR

Optimization

The AD9699 input buffer offers flexible controls for the analog

inputs, such as buffer current, dc coupling, and input full-scale

adjustment. All the available controls are shown in Figure 57.

Figure 57. Analog Input Controls

Using Register 0x1A4C and Register 0x1A4D, the buffer behavior

of the converter can be adjusted to optimize the SFDR over various

input frequencies and bandwidths of interest. Use Register 0x1910

to change the internal reference voltage. Changing the internal

reference voltage results in a change in the input full-scale voltage.

When the input buffer current in Register 0x1A4C and Regis-

ter 0x1A4D is set, the amount of current required by the AVDD3

supply changes. This relationship is shown in Figure 58. For a

complete list of buffer current settings, see Table 44.

Figure 58. AVDD3 Current (IAVDD3) vs. Buffer Current Setting (Buffer Control 1

Setting in Register 0x1A4C and Buffer Control 2 Setting in Register 0x1A4D)

Table 10 shows the recommended values for the buffer current for

various Nyquist zones.

Table 10. SFDR Optimization for Input Frequencies

Frequency

DC to 1500 MHz

400 µA/500 µA

1500 MHz to 3000 MHz

500 µA

>3000 MHz

500 µA/700 µA

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