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AD9699 Datasheet(PDF) 8 Page - Analog Devices |
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AD9699 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 121 page  Data Sheet AD9699 SPECIFICATIONS analog.com Rev. 0 | 8 of 121 SWITCHING SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD = 1.9 V, specified maximum sampling rate, 1.54 V p-p full-scale differential input, AIN = −2.0 dBFS, default SPI settings, and −20°C ≤ TJ ≤ +100°C, unless otherwise noted. The TJ range of −20°C to +100°C translates to a TA range of −40°C to +85°C. Typical specifications represent performance at TJ = 40°C (TA = 25°C). Table 4. Parameter Min Typ Max Unit CLOCK Clock Rate (at CLK+ and CLK− Pins) 3 6 GHz Sample Rate1 2500 3000 3100 MSPS Clock Pulse Width High 161.29 166.67 192.31 ps Clock Pulse Width Low 161.29 166.67 192.31 ps OUTPUT PARAMETERS Unit Interval (UI)2 62.5 66.67 592.6 ps Rise Time (tR) (20% to 80% into 100 Ω Load) 26 ps Fall Time (tF) (20% to 80% into 100 Ω Load) 26 ps Phase-Locked Loop (PLL) Lock Time 5 ms Data Rate per Channel (Nonreturn to Zero)3 1.6875 15 16 Gbps LATENCY4 Pipeline Latency5 75 Clock cycles Fast Detect Latency 26 Clock cycles WAKE-UP TIME Standby 400 µs Power-Down 15 ms NCO CHANNEL SELECTION TO OUTPUT 8 Clock cycles APERTURE Aperture Delay (tA) 250 ps Aperture Uncertainty (Jitter, tJ) 55 fs rms Out of Range Recovery Time 1 Clock cycles 1 The maximum sample rate is the clock rate after the divider. 2 Baud rate = 1/UI. A subset of this range can be supported. 3 Default L = 8. This number can be changed based on the sample rate and decimation ratio. 4 No DDCs used. L = 8, M = 2, and F = 1. 5 Refer to the End to End Total Latency section for more details. TIMING SPECIFICATIONS Table 5. Parameter Description Min Typ Max Unit CLK+ to SYSREF+ TIMING REQUIREMENTS tSU_SR Device clock to SYSREF+ setup time −65 ps tH_SR Device clock to SYSREF+ hold time 95 ps SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK must be in a logic high state 10 ns |
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