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Data Sheet

AD9699

ADC OVERRANGE AND FAST DETECT

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Rev. 0 | 29 of 121

In receiver applications, it is desirable to have a mechanism to

reliably determine when the converter is about to be clipped. The

standard overrange bit in the JESD204B outputs provides informa-

tion on the state of the analog input that is of limited usefulness.

Therefore, it is helpful to have a programmable threshold below full

scale that allows time to reduce the gain before the clip actually

occurs. In addition, because input signals can have significant slew

rates, the latency of this function is of major concern. Highly pipe-

lined converters can have significant latency. The AD9699 contains

fast detect circuitry to monitor the threshold and assert the FD pin.

ADC OVERRANGE

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange indicator can be

embedded within the JESD204B link as a control bit (when CSB

> 0). The latency of this overrange indicator matches the sample

latency.

The AD9699 also records any overrange condition in any of the

eight virtual converters. For more information on the virtual con-

verters, refer to Figure 81. The overrange status of each virtual

converter is registered as a sticky bit in Register 0x0563. The

contents of Register 0x0563 can be cleared using Register 0x0562,

by toggling the bits corresponding to the virtual converter to set and

reset position.

FAST THRESHOLD DETECTION (FD)

The FD pin is immediately set whenever the absolute value of

the input signal exceeds the programmable upper threshold level.

The FD bit is only cleared when the absolute value of the input

signal drops below the lower threshold level for greater than the

programmable dwell time. This feature provides hysteresis and

prevents the FD bit from excessively toggling.

The operation of the upper threshold and lower threshold registers,

along with the dwell time registers, is shown in Figure 75.

The FD indicator is asserted if the input magnitude exceeds the

value programmed in the fast detect upper threshold registers,

located at Register 0x0247 and Register 0x0248. The selected

threshold register is compared with the signal magnitude at the

output of the ADC. The fast upper threshold detection has a latency

of 28 clock cycles (maximum). The approximate upper threshold

magnitude is defined by

Upper Threshold Magnitude (dBFS) = 20log(Threshold Magni-

tude/213)

The FD indicators are not cleared until the signal drops below the

lower threshold for the programmed dwell time. The lower threshold

is programmed in the fast detect lower threshold registers, located

at Register 0x0249 and Register 0x024A. The fast detect lower

threshold register is a 13-bit register that is compared with the

signal magnitude at the output of the ADC. This comparison is

subject to the ADC pipeline latency, but is accurate in terms of

converter resolution. The lower threshold magnitude is defined by

Lower Threshold Magnitude (dBFS) = 20log(Threshold Magni-

tude/213)

For example, to set an upper threshold of −6 dBFS, write 0xFFF to

−10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A.

The dwell time can be programmed from 1 to 65,535 sample clock

cycles by placing the desired value in the fast detect dwell time

registers, located at Register 0x024B and Register 0x024C. See

Memory Map Register Details for more details.

Figure 75. Threshold Settings for FD Signal

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