AD9699 datasheet(40/121 Pages) AD

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

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Rev. 0 | 40 of 121

Only one NCO channel is active at a time and NCO channel

selection is controlled either by the CMOS GPIO pins or through the

Each NCO channel selector supports three different modes, descri-

bed as follows:

►

GPIO level control mode. In this mode, the GPIO pins determine

the exact NCO channel selected.

►

GPIO edge control mode. A low to high transition on a single

GPIO pin determines the exact NCO channel selected. The

internal channel selection counter is reset by either SYSREF± or

by the DDC soft reset.

►

determined directly through the register map.

The following procedure must be followed to use GPIO level control

mode for NCO channel selection:

1. Configure one or more GPIO pins as NCO channel selection

inputs. The GPIO pins not configured as NCO channel selection

inputs are internally tied low.

a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to 0x6

and Bits[3:0] in Register 0x0041 to 0x0.

b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to 0x6

and Bits[7:4] in Register 0x0041 to 0x0.

c. To use GPIO_A1, write Bits[3:0] in Register 0x0042 to 0x0.

d. To use GPIO_B1, write Bits[7:4] in Register 0x0042 to 0x0.

2. Configure the NCO channel selector in GPIO level control

mode by setting Bits[7:4] in the NCO control registers (Regis-

ter 0x0314, Register 0x0334, Register 0x0354, and Register

0x0374) to 0x1 through 0x6, depending on the desired GPIO

pin order.

3. Select the desired NCO channel through the GPIO pins.

The following procedure must be followed to use GPIO edge control

mode for NCO channel selection:

1. Configure one or more GPIO pins as NCO channel selection

inputs.

a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to 0x6

and Bits[3:0] in Register 0x0041 to 0x0.

b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to 0x6

and Bits[7:4] in Register 0x0041 to 0x0.

c. To use GPIO_A1, write Bits[3:0] in Register 0x0042 to 0x0.

d. To use GPIO_B1, write Bits[7:4] in Register 0x0042 to 0x0.

2. Configure the NCO channel selector in GPIO edge control

mode by setting Bits[7:4] in the NCO control registers (Regis-

ter 0x0314, Register 0x0334, Register 0x0354, and Register

0x0374) to 0x8 through 0xB, depending on the desired GPIO

pin.

3. Configure the wrap point for the NCO channel selection by

setting Bits[3:0] in the NCO control registers (Register 0x0314,

value of 4 causes the channel selection to wrap at Channel 4

(for example, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4).

4. Transition the selected GPIO pin from low to high to increment

the NCO channel selection.

Figure 86 shows an example use case for coherent mode using

three NCO channels. In this example, NCO Channel 0 is actively

downconverting Bandwidth 0 (B0), while NCO Channel 1 and

Channel 2 are in standby mode and are tuned to Bandwidth 1 and

Bandwidth 2 (B1 and B2), respectively.

The phase coherent NCO switching feature allows an infinite num-

ber of frequency hops that are all phase coherent. The initial phase

of the NCO is established at time t0 from SYSREF± synchroniza-

tion. Switching the NCO FTW does not affect the phase. With this

feature, only one FTW is required, but the user may wish to use all

16 channels to queue up the next hop.

After SYSREF± synchronization at startup, all NCOs across multi-

ple chips are inherently synchronized.

Figure 86. NCO Coherent Mode with Three NCO Channels (B0 Selected)

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