ADF7024 datasheet(11/24 Pages) AD

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Data Sheet

ADF7024

TIMING SPECIFICATIONS

VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, VGND = GND = 0 V, TA = TMIN to TMAX, unless otherwise noted.

Table 8. SPI Interface Timing

Parameter

Limit

Unit

Test Conditions/Comments

ns min

CS low to SCLK setup time

ns min

SCLK high time

ns min

SCLK low time

170

ns min

SCLK period

ns max

SCLK falling edge to MISO delay

ns min

MOSI to SCLK rising edge setup time

ns min

MOSI to SCLK rising edge hold time

ns min

SCLK falling edge to CS hold time

t11

270

ns min

CS high time

t12

310

µs typ

CS low to MISO high wake-up time, 26 MHz crystal with 7 pF load capacitance, TA = 25°C

t13

ns max

SCLK rise time

t14

ns max

SCLK fall time

t15

µs max

Initialization time; do not issue a command during this time; alternatively, poll the status

word and wait for the CMD_READY bit to go high

Timing Diagrams

Figure 2. SPI Interface Timing

Figure 3. PHY_SLEEP to SPI Ready State Timing (SPI Ready t12 After the Falling Edge of CS)

t11

t13

t14

SCLK

MISO

MOSI

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BIT 7

BIT 0

BIT 7

SPI STATE

SCLK

MISO

SLEEP

WAKE UP

SPI READY

t12

t15

Rev. B | Page 11 of 24

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