ADF7024 datasheet(22/24 Pages) AD

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ADF7024

Data Sheet

Crystal Oscillator

A 26 MHz crystal oscillator operating in parallel mode must be

connected between the XOSC26P and XOSC26N pins to provide

a reference for the ADF7024. Two parallel loading capacitors

are required for oscillation at the correct frequency. Their values

are dependent upon the crystal specification.

Transmitter

The ADF7024 supports binary frequency shift keying (FSK) and

binary level Gaussian filtered FSK (GFSK) modulation. For GFSK

modulation, the Gaussian filter uses a fixed BT of 0.5.

The ADF7024 PA has a single-ended output that can deliver up

to 13.5 dBm of output power. The output power can be set with

a typical resolution of 0.5 dB. The PA has built-in up and down

ramping, which reduces spectral splatter.

Receiver

The ADF7024 is based on a fully integrated, low IF receiver

architecture. The differential LNA is followed by a quadrature

downconversion mixer that converts the RF signal to the IF

frequency of 200 kHz (for IF filter bandwidths of 100 kHz and

200 kHz) or 300 kHz (for IF filter bandwidths of 300 kHz). The

IF filter bandwidth is configured to 100 kHz, 200 kHz, or 300 kHz,

depending on the radio profile selected. The bandwidth and center

frequency of the IF filter are calibrated automatically.

The IF filter gives excellent interference suppression of adjacent

and neighboring channels while also suppressing the image

channel. The ADF7024 is capable of providing improved

receiver image rejection performance by the use of a fully

integrated image rejection calibration system.

A correlator demodulator is used for demodulation. An

oversampled digital clock and data recovery (CDR) PLL is used

to resynchronize the received bit stream to a local clock.

RADIO PROFILES

The ADF7024 radio profiles provide a set of optimized register

settings for the ADF7024 radio. There are six radio profiles in

total, as shown in Table 1. The profiles cover common data rates

and modulation options. For further information on the ADF7024

radio profiles, see the ADF7024 Hardware Reference Manual,

UG-698, which is only available as part of the ADF7024 design

resource package.

PACKET MANAGEMENT

The ADF7024 includes comprehensive transmit and receive

packet management capabilities and can be configured for use

with a wide variety of packet-based radio protocols. There are

240 bytes of dedicated packet RAM available to store, transmit,

and receive packets. In transmit mode, a preamble, sync word,

and CRC can be added by the ADF7024 to the payload data

stored in the packet RAM. In addition, all packet data after the

sync word can be optionally whitened, Manchester encoded, or 8-

bit/10-bit encoded on transmission and decoded on reception.

In receive mode, the ADF7024 can qualify received packets

based on preamble detection, sync word detection, or CRC

validation and generate an interrupt on the IRQ_GP3 pin. On

reception of a valid packet, the received payload data is loaded to

packet RAM memory.

SMART WAKE MODES

The ADF7024 can be configured to operate in a broad range of

energy sensitive applications where battery lifetime is critical.

This includes support for applications where the ADF7024 is

required to operate in a fully autonomous mode or applications

where the host processor controls the transceiver during low power

mode operation. These low power modes are implemented using a

hardware WUC, a firmware timer, and the SWM functionality.

The combination of the low power WUC, the firmware timer,

and the SWM allows the ADF7024 to wake up autonomously

from sleep without intervention from the host processor. This

functionality allows carrier sense, packet sniffing, and packet

reception while the host processor is in sleep, thereby dramatically

reducing overall system current consumption. The SWM can

then wake the host processor on an interrupt condition.

Rev. B | Page 22 of 24

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