MAX8772 datasheet(36/47 Pages) MAXIM

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MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

______________________________________________________________________________________

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES

inhibits switching until VCC rises above 4.25V. The con-

troller powers up the reference once the system

enables the controller, VCC above 4.25V and SHDN dri-

ven high. With the reference in regulation, the controller

ramps the output voltage to the 1.20V boot voltage at

1/8 the slew rate set by RTIME:

where dVTARGET/dt = 12.5mV/µs x 71.5k

Ω / RTIME is the

slew rate. The soft-start circuitry does not use a variable

current limit, so full output current is available immediate-

ly. CLKEN is pulled low approximately 60µs after the

MAX8770/MAX8771/MAX8772 reach the boot voltage. At

the same time, the MAX8770/MAX8771/MAX8772 slew

the output to the voltage set at the VID inputs at the pro-

grammed slew rate. PWRGD and PHASEGD become

high impedance approximately 5ms after CLKEN is

pulled low. The MAX8770/MAX8771/MAX8772 automati-

cally use forced-PWM operation during soft-start and

soft-shutdown, regardless of the DPRSLPVR and PSI

configuration.

For automatic startup, the battery voltage should be

present before VCC. If the controller attempts to bring

the output into regulation without the battery-voltage

present, the fault latch trips. The controller remains shut

down until the fault latch is cleared by toggling SHDN

or cycling the VCC power supply below 0.5V.

If the VCC voltage drops below 4.25V, the controller

assumes that there is not enough supply voltage to

make valid decisions. To protect the output from over-

voltage faults, the controller shuts down immediately

and forces a high-impedance output.

Shutdown

When SHDN goes low, the MAX8770/MAX8771/MAX8772

enter low-power shutdown mode. CLKEN is pulled high

and PWRGD is pulled low immediately, and the output

voltage ramps down at 1/8 the slew rate set by RTIME:

where dVTARGET/dt = 12.5mV/µs x 71.5k

Ω / RTIME is

the slew rate. Slowly discharging the output capacitors

by slewing the output over a long period of time keeps

the average negative inductor current low (damped

response), thereby eliminating the negative output-volt-

age excursion that occurs when the controller dis-

charges the output quickly by permanently turning on

the low-side MOSFET (underdamped response). This

eliminates the need for the Schottky diode normally

connected between the output and ground to clamp

the negative output-voltage excursion. After the con-

troller reaches the zero target, the MAX8770/

MAX8771/MAX8772 shut down completely—the drivers

are disabled (DL1 and DL2 driven high)—the reference

turns off, and the supply currents drop to about 1µA

(max) 20µs.

When a fault condition—output UVLO or thermal shut-

down—activates the shutdown sequence, the protection

circuitry sets the fault latch to prevent the controller from

restarting. To clear the fault latch and reactivate the con-

troller, toggle SHDN or cycle VCC power below 0.5V.

Power Monitor (POUT)

The MAX8770/MAX8771/MAX8772 include a single-

quadrant multiplier used to determine the actual output

power based on the inductor current (sum of the differ-

ential CS inputs) and output voltage (CSNpm to GNDS,

when CSNpm = CSN12 for MAX8771, CSNpm = CSN2

for MAX8770/MAX8772). The buffered output of this

multiplier is connected to POUT and provides a voltage

relative to the output power dissipation:

where the power-monitor scale factor (KPWR) is typical-

ly 16.67mV. The power monitor allows the system to

accurately monitor the CPU’s power dissipation and

quickly predict if the system is about to overheat before

the significantly slower temperature sensor signals an

overtemperature alert.

Phase Fault (PHASEGD, MAX8771 Only)

The MAX8771 includes a phase-fault output that sig-

nals the system that one of the two phases either has a

fault condition or is not matched with the other.

Detection is done by identifying the need for a large on-

time difference between phases in order to achieve or

move towards current balance. PHASEGD is forced low

when VCCI is below 0.6xVFB or above 1.4xVFB.

PHASEGD is high impedance when the MAX8771 is set

to run in 1-phase operation (DPRSLPVR high, or PSI

low and DPRSLPVR low). On exit to the 2-phase mode,

PHASEGD is forced high impedance for 32 switching

cycles on DH2.

PHASEGD is low in shutdown. PHASEGD is forced high

impedance whenever the slew rate controller is active

(output voltage transitions).

Vpm

PWR

CSN

GNDS

LOAD SENSE

PWR

−

()(

)

TRAN SHDN

OUT

TARGET

()

= ()

TRAN START

BOOT

TARGET

()

= ()

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