MAX8772 datasheet(4/47 Pages) MAXIM

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MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

_______________________________________________________________________________________

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_

= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PWRGD, PHASEGD Startup

Delay

tPWRGD

Measured at startup from the time when

CLKEN goes low

358

Measured at FB with

respect to unloaded

output voltage

Lower threshold, falling

edge (undervoltage)

-350

-300

-250

CLKEN, PWRGD Threshold

15mV hysteresis (typ)

Upper threshold, rising

edge (overvoltage)

+150

+200

+250

CLKEN, PWRGD, PHASEGD

Delay

FB forced 25mV outside the PWRGD trip

thresholds

µs

CLKEN, PWRGD, PHASEGD

Transition Blanking Time

tBLANK

Measured from the time when FB reaches the

target voltage based on the slew rate set by

RTIME

µs

PHASEGD Transition Blanking

Time

tPHASEGD

Number of DH2 pulses from when phase 2 is

enabled

Cycles

V(CCI, FB),

0.4V

≤ V(FB) ≤ 1.5V

Lower threshold,

0.6VFB nominal

-20

+20

PHASEGD Window

Comparator Thresholds

15mV hysteresis (typ)

Upper threshold,

1.4VFB nominal

-20

+20

CLKEN, PWRGD, PHASEGD

Output Low Voltage

ISINK = 3mA

0.4

CLKEN, PWRGD, PHASEGD

Leakage Current

High state, CLKEN, PWRGD, PHASEGD forced

to 5V

1µA

VRHOT Trip Threshold

Measured at THRM, with respect to VCC; falling

edge, 115mV hysteresis (typ)

29.5

30.5

VRHOT Delay

tVRHOT

THRM forced 25mV below the VRHOT trip

threshold; falling edge

µs

VRHOT Output On-Resistance

RVRHOT

Low state

3.5

Ω

VRHOT Leakage Current

High state. VRHOT forced to 5V

µA

THRM Input Leakage

-100

+100

VCC Undervoltage Lockout

Threshold

VUVLO(VCC)

Rising edge, 50mV hysteresis, DL_ pulled low

below this level

4.1

4.25

4.45

VCC Power-On Reset

Threshold

Falling edge, typical hysteresis = 1.1V, faults

cleared and DL_ forced high when VCC falls

below this level

1.8

Thermal Shutdown Threshold

TSHDN

Hysteresis = 15

°C

160

°C

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