MAX8772 datasheet(40/47 Pages) MAXIM

40 / 47 page

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

______________________________________________________________________________________

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES

Output Capacitor Selection

The output filter capacitor must have low enough ESR to

meet output ripple and load-transient requirements, yet

have high enough ESR to satisfy stability requirements.

In CPU VCORE converters and other applications where

the output is subject to large load transients, the output

capacitor’s size typically depends on how much ESR is

needed to prevent the output from dipping too low

under a load transient. Ignoring the sag due to finite

capacitance:

In non-CPU applications, the output capacitor’s size

often depends on how much ESR is needed to maintain

an acceptable level of output ripple voltage. The output

ripple voltage of a step-down controller equals the total

inductor ripple current multiplied by the output capaci-

tor’s ESR. When operating multiphase systems out-of-

phase, the peak inductor currents of each phase are

staggered, resulting in lower output ripple voltage by

reducing the total inductor ripple current. For multi-

phase operation, the maximum ESR to meet ripple

requirements is:

where

ηTOTAL is the total number of active phases and

fSW is the switching frequency per phase. The actual

capacitance value required relates to the physical size

needed to achieve low ESR, as well as to the chemistry

of the capacitor technology. Thus, the capacitor is usu-

ally selected by ESR and voltage rating rather than by

capacitance value (this is true of polymer types).

When using low-capacity ceramic filter capacitors,

capacitor size is usually determined by the capacity

needed to prevent VSAG and VSOAR from causing

problems during load transients. Generally, once

enough capacitance is added to meet the overshoot

requirement, undershoot at the rising load edge is no

longer a problem (see the VSAG and VSOAR equations

in the Transient Response section).

Output Capacitor Stability Considerations

For Quick-PWM controllers, stability is determined by

the value of the ESR zero relative to the switching

frequency. The boundary of instability is given by the

following equation:

where:

where COUT is the total output capacitance, RESR is the

total ESR, RSENSE is the current-sense resistance (RCM

= RCS), RDROOP is the voltage-positioning gain, and

RPCB is the parasitic board resistance between the out-

put capacitors and sense resistors.

For a standard 300kHz application, the ESR zero fre-

quency must be well below 95kHz, preferably below

50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP

capacitors in widespread use at the time of publication

have typical ESR zero frequencies below 50kHz. In the

standard application circuit, the ESR needed to support

a 30mVP-P ripple is 30mV/(40A x 0.3) = 2.5m

Ω. Four

330µF/2.5V Panasonic SP (type SX) capacitors in paral-

lel provide 1.5m

Ω (max) ESR. With a 2mΩ droop and

0.5m

Ω PC board resistance, the typical combined ESR

results in a zero at 30kHz.

Ceramic capacitors have a high ESR zero frequency,

but applications with significant voltage positioning can

take advantage of their size and low ESR. Do not put

high-value ceramic capacitors directly across the output

without verifying that the circuit contains enough voltage

positioning and series PC board resistance to ensure

stability. When only using ceramic output capacitors,

output overshoot (VSOAR) typically determines the mini-

mum output capacitance requirement. Their relatively

low capacitance value can cause output overshoot

when stepping from full-load to no-load conditions,

unless a small inductor value is used (high switching

frequency) to minimize the energy transferred from

inductor to capacitor during load-step recovery. The

efficiency penalty for operating at 600kHz is approxi-

mately 5% when compared to the 300kHz circuit, pri-

marily due to the high-side MOSFET switching losses.

and

RRR

ESR

EFF OUT

EFF

ESR

DROOP

PCB

ESR

≤

ESR

IN SW

TOTAL OUT

OUT

RIPPLE

≤

−

()

⎡

⎣

⎢

⎤

⎦

⎥

ESR

PCB

STEP

LOAD MAX

()

() ≤

∆

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