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FEATURES

SPECIFICATIONS

DESCRIPTION

LPCC−48 PACKAGE

(TOP VIEW)

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CP2O

LD2

LF2

DATA

CLK

VCCD2

FR

VCCD1

FRBP

EN

LF1

LD1

36

35

34

33

32

31

30

29

28

27

26

25

EXTLO2IP

EXTLO2IN

TXON

IFOP

VCCIF

IFON

GND

GND

GAIN[4]

GAIN[3]

GAIN[2]

GAIN[1]

TRF1121

TRF1221

SLWS170A – APRIL 2005 – REVISED DECEMBER 2005

Dual VCO/PLL Synthesizer With IF Up-Converter

The TRF1121/TRF1221 are designed to function as

part of complete 2.5-GHz and 3.5-GHz radio chipsets,

•

Low Phase Noise

respectively. In the chipset, the transmit chain

•

Image Reject Upconverter

operates as a double up converter from an IF

frequency input (typically from a baseband modem's

•

Dual VCO/PLL For Double Up Conversion

DAC) to an RF output frequency. The TRF1121/

Architecture

TRF1221 performs the first up conversion from IF

•

On-Chip VCO, Resonator and PLL Only

signals in the range of 10 MHz to 60 MHz to a

Requires Off-Chip Loop Filter

second IF frequency in the range of 300 MHz to 360

•

External S-Band VCO Option

MHz. The radio chipset features sufficient linearity,

phase noise, and dynamic range to work in either

•

5-Bit Transmit Level Control, 32 dB in 1 dB

single

carrier

or

multi-carrier,

line-of-sight

or

Steps

non-line-of-sight,

standard

(IEEE

802.16),

or

proprietary systems. Due to the modular nature of the

chipset, it is ideal for use in systems that employ

•

S-Band LO Frequency Range:

transmit or receive diversity.

– TRF1121: 1500 to 2500 MHz

– TRF1221: 1700 to 3600 MHz

•

UHF LO Frequency Range: 250 to 350 MHz

•

Input Frequency Range: 10 MHz to 70 MHz

•

S-Band LO Phase Noise Typical 0.5 rms (100

Hz to 1 MHz)

•

Output Power Range From –32 dBm to 0 dBm

in 1 dB Steps (500-mVpp Diff Input)

•

Minimum UHF LO Step Size of 50 kHz For

TRF1121 and 62.5 kHz for TRF1221

•

Image Rejection: –50 dBc, Typical (20–40 MHz

Tx IF Input)

•

LO Leakage: –36 dBm, Typical

•

The TRF1121/TRF1221 are VHF-UHF upconverters

with

integrated

UHF

and

S-band

frequency

synthesizers for radio applications in the 2GHz to 4

GHz range. The IC performs the first up-conversion

and generates the local oscillator (LO) for the second

up-conversion. The device uniquely integrates an

image reject mixer, IF gain blocks, 5-bit gain control,

and two complete phase locked loop (PLL) circuits

including: VCOs, resonator circuit, varactors, dividers,

and phase detectors.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2005, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.