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A[7]=MSB

A[6]

A[5]

D[1]

Data

Clock

EN

E

PWH

C

PWL

C

PWH

D[0] LSB

A[4]

CD

I

D

CE

L

E

Fout

+ REFIN

8

(N

) 3) * S *

F

18

[2

M]

(1)

Fout

+ REFIN

8

(N

) 3) * S *

F

18

(2)

TRF1121

TRF1221

SLWS170A – APRIL 2005 – REVISED DECEMBER 2005

Figure 7. Serial Interface Timing Diagram

Data is written to the PLLs according to the format in Figure 8.

MSB

Byte 1

LSB

MSB

Byte 2

LSB

MSB

Byte 3

LSB

Address

Data

A[7]

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

A[0]

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

1

0

0

0

0

0

0

0

0

0

Synth #1 N divider

Synth #1 S counter

Synth #1 F counter

1

0

0

0

0

0

0

1

0

0

Synth #2 N divider

Synth #2 S counter

Synth #2 F counter

1

0

0

0

0

1

0

0

0

0

0

0

0

0

0

PS

0

0

0

0

0

0

0

0

all other addresses reserved for future expansion

Figure 8. Serial Interface Data Format

The first eight bits are the appropriate address for the instruction set and the remaining 16 bits are the

instructions. The data is 24 bits long (3 bytes). Byte 1 is the address with A[7] being the MSB and A[0] being the

LSB. Byte 2 and 3 program the IC with synthesizer information and PS (Polarity Select Bit) information. D[15] is

the MSB and D[8] the LSB. The PS bit selects which edge of the reference is used for frequency comparison.

Improved spurious and phase noise is achieved by selecting the edge with the fastest rise or fall time. If PS = 1

the rising edge is used as the reference. If PS = 0, the falling edge is used.

Figure 7 needs to be sent to the TRF1121 / TRF1221 to fully program the Synthesizers #1 and #2 and the PS

bit. Once the synthesizers and the PS bit are fully programmed, the clock signal should be turned off to eliminate

any clock-related spurious signals.

The LO1 (UHF oscillator) frequency of oscillation is set by Equation 1:

where M = 10 for TRF1121 and 8 for 1221

The TRF1121/TRF1221 contains two independent S-band VCOs and resonator circuits to provide additional

frequency range from one IC, however only one VCO can be enabled at a time. These two VCOs are referred to

as VCO2A and VCO2B (see the block diagram). The S-band PLL (LO2A or LO2B) frequency of oscillation is set

by the following equation:

where F has a range of 0 to 17. Both N and S have ranges that are limited more by the LO range than by their

digital count.

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