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TRF1121

TRF1221

SLWS170A – APRIL 2005 – REVISED DECEMBER 2005

TERMINAL FUNCTIONS

TERMINAL

I/O

TYPE

DESCRIPTION

NO.

NAME

1

CP2O

O

Analog

Synthesizer 2 charge pump output

2

LD2

O

Digital

Synthesizer 2 lock detect output, High is locked.

3

LF2

O

Analog

Lock detect filter capacitor for LO2, 0.01

4

DATA

I

Digital

Serial interface data input

5

CLK

I

Digital

Serial interface clock input

6

VCCD2

I

Power

+5 V power for digital

7

FR

I

Analog

18-MHz reference clock input, HCMOS input. (DC level = 2.5 V)

8

VCCD1

I

Power

+5 V power for digital

9

FRBP

O

Analog

Reference frequency bypass. Internally biased to 2.5 V.

10

EN

I

Digital

Serial interface load enable (active high)

11

LF1

O

Analog

Lock detect filter capacitor for LO1, 0.01

12

LD1

O

Digital

Synthesizer 1 lock detect output, High is locked.

13

CP1O

O

Analog

Synthesizer 1 charge pump output

14

LO1BPA

O

Analog

Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to

any other pin.

15

LO1TUN

I

Analog

VCO synthesizer 1 tuning port

16

LO1BPB

O

Analog

Bypass capacitor for LO1 0.1

µF (min) DCV =1.0 V

17

VCCLO1

I

Power

VCC for LO1

18, 19, 20, 29, GND

Power

Ground

30, 37, 39, 42

21

BBIN

I

Analog

Baseband IF input (2 k

Ω diff) negative, dc-coupled, Internal voltage is 4 V DC

22

BBIP

I

Analog

Baseband IF input (2 k

Ω diff) positive, dc-coupled, Internal voltage is 4 V DC

23

VCCUPC

I

Power

+5V power Analog

24

GAIN[0]

I

Digital

Gain control bit 0 (LSB) – Logic low induces 1-dB attenuation

25

GAIN[1]

I

Digital

Gain control bit 1 – Logic low induces 2-dB attenuation

26

GAIN[2]

I

Digital

Gain control bit 2 – Logic low induces 4-dB attenuation

27

GAIN[3]

I

Digital

Gain control bit 3 – Logic low induces 8-dB attenuation

28

GAIN[4]

I

Digital

Gain control bit 4 (MSB) – Logic low induces 16-dB attenuation

31

IFON

O

Analog

IF analog output (100

Ω diff ) negative, dc-coupled, Internal voltage is 2.1 V DC

32

VCCIF

I

Power

+5 V power Analog

33

IFOP

O

Analog

IF analog output (100

Ω diff ) positive, dc-coupled, Internal voltage is 2.1 V DC

34

TXON

I

Digital

IF amplifier enable active high

35

EXTLO2IN

I

Analog

External input for LO2 (differential) negative and logic level for VCO select.

36

EXTLO2IP

I

Analog

External input for LO2 (differential) positive and logic level for VCO select.

38

VCCLO2

I

Power

VCC for LO2 A and B

40

LO2ON

O

Analog

LO2 output (differential) Negative and positive VCC bias (+5 V) for LO buffer amp.

41

LO2OP

O

Analog

LO2 output (differential) Positive and positive VCC bias (+5 V) for LO buffer amp.

43

LO2BBPA

O

Analog

Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to

any other pin.

44

LO2BTUN

I

Analog

LO2B Tune Port

45

LO2BBPB

O

Analog

Bypass cap. for LO2B 0.1

µF (min) DCV = 1 V

46

LO2ABPA

O

Analog

Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to

any other pin.

47

LO2ATUN

I

Analog

LO2A tune port

48

LO2ABPB

O

Analog

Bypass capacitor for LO2A 0.1

µF (min ) DCV = 1 V

Back

Back side of package has metal base that must be grounded for thermal and RF performance

(1)

Current leakage on the order of 10

µA through the capacitor or by any other means from either LF pin can cause false loss of lock

signals. The two pullup resistors (R16 and R17) in Figure 23 reduce this sensitivity.

3