LTC4292 datasheet(32/40 Pages) AD

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LTC4291-1/LTC4292

Rev 0

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If the LTC4291-1 is asserting INT, it will also respond to

the alert response address (0001100b) per the SMBus

specification.

Each LTC4291-1/LTC4292 is logically composed of a

single four port quad, packed into a single I2C address.

Interrupts and SMBAlert

Most port events can be configured to trigger an inter-

rupt, asserting INT and alerting the host to the event. This

removes the need for the host to poll the LTC4291-1,

minimizing serial bus traffic and conserving host CPU

cycles. Multiple LTC4291-1s can share a common INT

line, with the host using the SMBAlert protocol (ARA) to

determine which LTC4291-1 caused an interrupt.

For information on serial bus usage and device con-

figuration and status, refer to the LTC4291 Software

Programming documentation. Contact Analog Devices

to request this document.

ISOLATION REQUIREMENTS

IEEE 802.3 Ethernet specifications require that network

segments (including PoE circuitry) be electrically isolated

from the chassis ground of each network interface device.

However, network segments are not required to be iso-

lated from each other, provided that the segments are

connected to devices residing within a single building on

a single power distribution system.

For simple devices, such as small PoE switches, the isola-

tion requirement can be met by using an isolated main

power supply for the entire device. This strategy can be

used if the device has no electrically conducting ports

other than twisted-pair Ethernet. In this case, the SDAIN

and SDAOUT pins can be tied together and will act as a

standard I2C/SMBus SDA pin.

If the device is part of a larger system, contains additional

external non-Ethernet ports, or must be referenced to pro-

tective ground for some other reason, the PoE subsystem

must be electrically isolated from the rest of the system.

The LTC4291-1/LTC4292 chipset simplifies PSE isolation

by allowing the LTC4291-1 chip to reside on the non-

isolated side. There it can receive power from the main

logic supply and connect directly to the I2C/SMBus bus.

Isolation between the LTC4291-1 and LTC4292 is imple-

mented using a proprietary transformer-based commu-

nication protocol. Additional details are provided in the

Serial Bus Isolation section of this data sheet.

EXTERNAL COMPONENT SELECTION

Power Supplies

The LTC4291-1/LTC4292 requires two supply voltages to

operate. VDD requires 3.3V (nominally) relative to DGND.

VEE requires a negative voltage of between –51V to –57V

for Type 3 PSEs, or –53V to –57V for Type 4 PSEs, rela-

tive to AGNDP.

Digital Power Supply

VDD provides digital power for the LTC4291-1 processor.

A ceramic decoupling cap of at least 0.1μF should be

placed from VDD to DGND, as close as practical to each

LTC4291-1. A 1.8V core voltage supply is generated inter-

nally and requires a 1µF ceramic decoupling cap between

the CAP1 pin and DGND.

In the LTC4291-1, VDD should be delivered by the host

controller’s non-isolated 3.3V supply. To maintain required

isolation, LTC4292 AGNDP and LTC4291-1 DGND must

not be connected in any way.

Main PoE Power Supply

VEE is the main isolated PoE supply that provides power

to the PDs. Because it supplies a relatively large amount

of power and is subject to significant current transients,

it requires more design care than a simple logic supply.

For minimum IR loss and best system efficiency, set VEE

near maximum amplitude (57V), leaving enough margin

to account for transient over or undershoot, temperature

drift, and the line regulation specifications of the particular

power supply used.

APPLICATIONS INFORMATION

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