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LTC4292 Datasheet(PDF) 6 Page - Analog Devices

Part # LTC4292
Description  4-Port IEEE 802.3bt PoE PSE Controller
PDF  40 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTC4292 Datasheet(HTML) 6 Page - Analog Devices

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LTC4291-1/LTC4292
6
Rev 0
For more information www.analog.com
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tME1
Mark Event Duration (Except Last Mark
Event)
(Note 11)
l
6
8.6
12
ms
tME2
Last Mark Event Duration
(Note 11)
l
6
20
ms
tPON
Power On Delay, Auto Mode
From End of Valid Detect to End of Valid Inrush
(Note 14)
l
400
ms
tAUTO_PSE1
Autoclass Power Measurement Start
From End of Inrush to Beginning of Autoclass
Power Measurement
l
1.4
1.6
s
tAUTO_PSE2
Autoclass Power Measurement End
From End of Inrush to End of Autoclass Power
Measurement
l
3.1
3.5
s
tAUTO_WINDOW
Autoclass Average Power Sliding
Window
l
0.15
0.2
0.3
s
tED
Fault Delay
From Power On Fault to Next Detect
l
1.0
1.3
1.5
s
tSTART
Maximum Current Limit Duration
During Inrush
l
52
59
66
ms
tCUT
Maximum Overcurrent Duration After
Inrush
l
52
59
66
ms
Maximum Overcurrent Duty Cycle
l
5.8
6.3
6.7
%
tLIM
Maximum Current Limit Duration After
Inrush
(Note 12)
Type 3, tLIMn = 8h
Type 4, tLIMn = 5h
l
l
10
6
12
8
14
10
ms
ms
tMPS
Maintain Power Signature (MPS) Pulse
Width Sensitivity
Current Pulse Width to Reset Disconnect Timer
(Note 8)
l
1.6
3.6
ms
tDIS
Maintain Power Signature (MPS)
Dropout Time
(Note 5)
l
320
350
380
ms
tMSD
Masked Shut Down Delay
6.5
µs
I2C Watchdog Timer Duration
l
1.5
2
3
s
Minimum Pulse Width for Masked Shut
Down
l
3
µs
Minimum Pulse Width for RESET
l
4.5
µs
I2C Timing (Note 7)
fSCLK
Clock Frequency
l
1
MHz
t1
Bus Free Time
Figure 5 (Note 9)
l
480
ns
t2
Start Hold Time
Figure 5 (Note 9)
l
240
ns
t3
SCL Low Time
Figure 5 (Note 9)
l
480
ns
t4
SCL High Time
Figure 5 (Note 9)
l
240
ns
t5
SDAIN Data Hold Time
Figure 5 (Note 9)
l
60
ns
t5
Data Clock to SDAOUT Valid
Figure 5 (Note 9)
l
130
ns
t6
Data Set-Up Time
Figure 5 (Note 9)
l
80
ns
t7
Start Set-Up Time
Figure 5 (Note 9)
l
240
ns
t8
Stop Set-Up Time
Figure 5 (Note 9)
l
240
ns
tr
SCL, SDAIN Rise Time
Figure 5 (Note 9)
l
120
ns
tf
SCL, SDAIN Fall Time
Figure 5 (Note 9)
l
60
ns
Fault Present to INT Pin Low
(Notes 9, 10)
l
150
ns
Stop Condition to INT Pin Low
(Notes 9, 10)
l
1.5
µs
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGNDP – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)



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