LTC4292 datasheet(14/40 Pages) AD

14 / 40 page

LTC4291-1/LTC4292

Rev 0

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CPD (Pin 8): Clock Transceiver Positive Input Output

(Digital). Connect to CPA through a data transformer.

CND (Pin 9): Clock Transceiver Negative Input Output

(Digital). Connect to CNA through a data transformer.

DPD (Pin 10): Data Transceiver Positive Input Output

(Digital). Connect to DPA through a data transformer.

DND (Pin 11): Data Transceiver Negative Input Output

(Digital). Connect to DNA through a data transformer.

VDD (Pins 12, 20): VDD IO Power Supply. Connect to

a 3.3V power supply relative to DGND. VDD must be

bypassed to DGND near the LTC4291-1 with at least a

0.1μF capacitor.

RESET (Pin 14): Reset Input, Active Low. When RESET is

low, the LTC4291-1/LTC4292 is held inactive with all ports

off and all internal registers reset. When RESET is pulled

high, the LTC4291-1/LTC4292 begins normal operation.

RESET can be connected to an external capacitor or RC

network to provide a power turn-on delay. Internal filtering

of RESET prevents glitches less than 1μs wide from reset-

ting the LTC4291-1/LTC4292. Internally pulled up to VDD.

INT (Pin 15): Interrupt Output, Open Drain. INT will pull

low when any one of several events occur in the LTC4291-

1. It will return to a high impedance state when bits 6 or

7 are set in the Reset PB register (1Ah). The INT signal

can be used to generate an interrupt to the host proces-

sor, eliminating the need for continuous software polling.

Individual INT events can be disabled using the INT Mask

documentation for more information. INT is only updated

between I2C transactions.

SDAOUT (Pin 16): Serial Data Output, Open Drain Data

Output for the I2C Serial Interface Bus. The LTC4291-1

uses two pins to implement the bidirectional SDA func-

tion to simplify opto isolation of the I2C bus. To imple-

ment a standard bidirectional SDA pin, tie SDAOUT and

SDAIN together. See Applications Information for more

information.

SDAIN (Pin 17): Serial Data Input. High impedance data

input for the I2C serial interface bus. The LTC4291-1

uses two pins to implement the bidirectional SDA func-

tion to simplify opto isolation of the I2C bus. To imple-

ment a standard bidirectional SDA pin, tie SDAOUT and

SDAIN together. See Applications Information for more

information.

SCL (Pin 18): Serial Clock Input. High impedance clock

input for the I2C serial interface bus. The SCL pin should

be connected directly to the I2C SCL bus line. SCL must

be tied high if the I2C serial interface bus is not used.

CAP1 (Pin 19): Core Power Supply Bypass Capacitor.

Connect a 1µF capacitance to DGND for the internal 1.8V

regulator bypass. Do not use other capacitor values.

AUTO (Pin 21): Auto Mode Input, Active High. When high,

the LTC4291-1 detects, classifies and powers up valid

PDs without host interaction. AUTO determines the state

of the internal registers when the LTC4291-1 is reset or

comes out of UVLO (see LTC4291 Software Programming

documentation). The state of these register bits can sub-

sequently be changed via the I2C interface. Internally

pulled down to DGND.

GP1 (Pin 22): General Purpose Digital Input Output for

customer applications. Referenced to DGND.

GP0 (Pin 23): General Purpose Digital Input Output for

customer applications. Referenced to DGND.

MSD (Pin 24): Maskable Shutdown Input, Active Low.

When pulled low, all ports that have their corresponding

mask bit set in the mconf register (17h) will be reset.

Internal filtering of the MSD pin prevents glitches less

than 1μs wide from resetting ports. The MSD Pin Mode

pulled up to VDD.

DGND (Pin 5, Exposed Pad Pin 25): Digital Ground. DGND

should be connected to the return from the VDD supply.

PIN FUNCTIONS

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