LTC4292 datasheet(34/40 Pages) AD

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LTC4291-1/LTC4292

Rev 0

For more information www.analog.com

Sense Resistors

The LTC4291-1/LTC4292 is designed for a low 0.15Ω cur-

rent sense resistance per channel. Two parallel 0.3Ω resis-

tors must be laid out as shown in the Layout Requirements

section. In order to meet the IHOLD-2P, ICUT-2P, and ILIM-2P

accuracy required by the IEEE specification, the sense

resistors should have ±1% tolerance or better, and no

more than ±200ppm/°C temperature coefficient.

Port Output Cap

Each port requires a 0.22μF cap across OUTnM to AGNDP

(see Figure 25) to keep the LTC4292 stable while in cur-

rent limit during startup or overload. Common ceramic

capacitors often have significant voltage coefficients; this

means the capacitance is reduced as the applied voltage

increases. To minimize this problem, X7R ceramic capaci-

tors rated for at least 100V are recommended and must

be located close to the LTC4292.

Surge Protection

Ethernet ports can be subject to significant cable surge

events. To keep PoE voltages below a safe level and pro-

tect the application against damage, protection compo-

nents, as shown in Figure 26, are required at the main

supply, at the LTC4292 supply pins, and at each port.

Bulk transient voltage suppression (TVSBULK) and bulk

capacitance (CBULK) are required across the main PoE

supply and should be sized to accommodate system level

surge requirements.

Each LTC4292 requires a 10Ω, 0805 resistor (R1) in series

from supply AGND to the LTC4292 AGNDP pin. Across

Figure 26. LTC4292 Surge Protection

42911 F26

AGNDP

VEE

SENSEnM

VSSKn

GATEnM OUTnM

OUTnM

PORT

S1B

1µF

100V

LTC4292

SMAJ58A

10Ω

CBULK

TVSBULK

VEE

0.22µF

X7R

100V

QnM

RSENSEnM

AGNDP

the LTC4292 AGNDP pin and VEE pin is a SMAJ58A 58V

TVS (D1) and a 1µF, 100V bypass capacitor (C1). These

components must be placed close to the LTC4292 pins.

Finally, each port requires a pair of S1B clamp diodes: one

from OUTnM to supply AGND and one from OUTnM to

supply VEE. The diodes at the ports steer harmful surges

into the supply rails where they are absorbed by the surge

suppressors and the VEE bypass capacitance. The layout

of these paths must be low impedance.

LAYOUT REQUIREMENTS

Strict adherence to board layout, parts placement and

routing requirements is critical for IEEE compliance, para-

metric measurement accuracy, system robustness and

thermal dissipation. Refer to the DC2685A demo kit for

example layout references.

Sense Resistor Block Layout Requirements

A channel sense resistor may be affected by currents

flowing in other channels. To ensure IEEE parametric

compliance, the sense resistor layout is strictly defined

and must be adhered to. In addition, the sense resistor

block’s common VEE plane connections and layout are

specified.

Figure 33 shows the component names for ports 1 and 2

as referenced in the remainder of this section. The sense

resistors (RST1 to RST4 and RSU1 to RSU4) for channels

1A, 1B, 2A, and 2B must be grouped together in a sense

resistor block. The same requirements apply to channel

3A, 3B, 4A, and 4B sense resistors and VSSK34.

APPLICATIONS INFORMATION

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