FEDL7055-02

OKI Semiconductor

ML7055

15/30

• Timing in Long Mode and in PCMCLK and PCMSYNC Output mode

(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)

• Timing in Long Mode and in PCMCLK and PCMSYNC Input Mode.

(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)

DETACH Interface Block

• Generation of the request for change to (from) the stop mode by detection of the rising (falling) edge of

the

DETACH signal

MSB

DATA

DATA

DATA

DATA

LSB

DATA

MSB

8 bits or 16 bits

Data is output on the rising edge of CLK.

PCMCLK(I)

64k/128kHz

PCMOUT

MSB

DATA

DATA

DATA

DATA

LSB

DATA

MSB

PCMIN

Data is shifted in on the falling edge of CLK.

≥ PCMCLK period (Min.) or ≤ 62.5 µs (Max.)

125

µs (8kHz)

MSB

DATA

DATA

DATA

DATA

LSB

DATA

MSB

8 bits or 16 bits

Data is output on the rising edge of CLK

PCMCLK(O)

64k/128kHz

PCMSYNC(O)

PCMOUT

MSB

DATA

DATA

DATA

DATA

LSB

DATA

MSB

PCMIN

Data is shifted in on the falling edge of CLK

PCMCLK period

× 3

125

µs (8kHz)