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PC8374L Datasheet(PDF) 31 Page - National Semiconductor (TI) |
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PC8374L Datasheet(HTML) 31 Page - National Semiconductor (TI) |
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31 / 239 page ![]() 1.0 Signal/Pin Connection and Description (Continued) Revision 1.1 31 www.national.com GPO11 117 VSB3 PU30 Programmable1 GPO12-13 122, 125 VDD3 PU30 Programmable1 Glue Functions PWRGD_PS 82 VSB3 PU90 CPU_PRESENT 83 VSB3 PU90 PRIMARY_HD 67 VDD3 PU90 SECONDARY_HD 68 VDD3 PU90 SCSI 69 VDD3 PU90 Strap Configuration BADDR 30 VDD3 PU30 Strap7 TRIS 26 VDD3 PU30 Strap7 TEST 27 VDD3 PU30 Strap7 VsbStrap1 117 VSB3 PU30 Strap8 VddStrap1 122 VDD3 PU30 Strap7 VddStrap2 125 VDD3 PU30 Strap7 1. Default at reset: enabled. 2. Enabled only when the OD6 buffer type is selected (OD6 is the default at reset). 3. Alternate function at reset: enabled. 4. Default at reset: PD enabled. 5. Default at reset: disabled. 6. Alternate function at reset: disabled. 7. Active only during VDD Power-Up reset. 8. Active only during VSB Power-Up reset. Table 4. Internal Pull-Up and Pull-Down Resistors (Continued) Signal Pin(s) Power Well Type Comments Winbond Electronics Corp. Advanced PC Product Center |
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