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PC8374L Datasheet(PDF) 42 Page - National Semiconductor (TI) |
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PC8374L Datasheet(HTML) 42 Page - National Semiconductor (TI) |
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42 / 239 page ![]() 3.0 Device Architecture and Configuration (Continued) www.national.com 42 Revision1.1 3.2.4 Standard Configuration Registers Figure 5. Configuration Register Map Table 16. Special Logical Device Configuration Registers Index Register Name Description F0h-FFh Logical Device Configuration Special (vendor-defined) configuration options. SuperI/O Configuration Registers Logical Device Control and one per Logical Device Configuration Registers - Index Register Name 07h Logical Device Number 10h Memory Space Configuration 12h-13h Memory Base Address (MEM_BASE) 20h SuperI/O ID 21h SuperI/O Configuration 1 22h SuperI/O Configuration 2 23h SuperI/O Configuration 3 24h SuperI/O Configuration 4 25h Reserved 26h SuperI/O Configuration 6 27h SuperI/O Revision ID 28h Reserved 29h Clock Generator Control 2A Health Management SMBus Configuration 2Bh-2Dh Reserved 2Eh-2Fh Reserved exclusively for National use 30h Logical Device Control (Activate) 50h Memory Base Descriptor 60h I/O Base Address Descriptor 0 Bits 15-8 61h I/O Base Address Descriptor 0 Bits 7-0 62h I/O Base Address Descriptor 1 Bits 15-8 63h I/O Base Address Descriptor 1 Bits 7-0 70h Interrupt Number and Wake-Up on IRQ Enable 71h IRQ Type Select 74h DMA Channel Select 0 75h DMA Channel Select 1 F0h-FFh Vendor-Defined Logical Device Configuration (some are optional) Winbond Electronics Corp. Advanced PC Product Center |
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