PC8374L datasheet(48/239 Pages) NSC

48 / 239 page

3.0 Device Architecture and Configuration (Continued)

www.national.com

Revision1.1

3.3 MODULE CONTROL

Module control is performed primarily through the Activation bit (bit 0 of index 30h) of each logical device.

3.3.1

Module Enable/Disable

Module control is performed primarily through the Activation bit (bit 0 of index 30h) of each logical device. The operation of

each module can be controlled by the host.

Module enable/disable by the host through the LPC bus is controlled by the following bits:

● Activation bit (bit 0) in index 30h of the Standard configuration registers (see Section 3.2.3 on page 39)

● Fast Disable bit in SIOCF6 register; for the FDC, Parallel Port and Serial Port (1 and 2) / InfraRed Port modules only

(see Section 3.7.9 on page 57)

● Global Enable bit (GLOBEN) in SIOCF1 register (see Section 3.7.5 on page 54)

A module is enabled only if all of these bits are set to their “enable” value.

When a module is disabled, the following takes place:

● The host system resources of the logical device (IRQ, DMA and runtime address range) are unassigned.

● Access to the standard- and device-specific Logical Device configuration registers through the LPC bus remains enabled.

● Access to the module’s runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is

not generated).

Note that disabling a VDD3-powered module (FDC, Parallel Port, Serial Ports, InfraRed Port, KBC) stops the module’s inter-

nal clock to lower the power consumption; as a result, the module is not functional. VSB-powered modules remain functional.

3.3.2

Floating Module Output

The pins of the Legacy modules (Serial Ports, Parallel Port, Floppy Disk Controller, Keyboard and Mouse Controller) can be

floated. When the TRI-STATE Control bit (bit 0) is set in the specific module configuration register (at index F0h of the specific

Logical Device in the configuration space) and the module is disabled (see Section 3.3.1), the module output signals are floated

and the I/O signals are configured as inputs (note that the logic level at the inputs is ignored by the module, which is disabled).

Figure 9 shows the control mechanism for floating the pins of a Legacy module.

Figure 9. Control of Floating Legacy Module Pins

Fast

Disable

xxxDIS1

SIOCF6

TRI-

STATE

Control

Conﬁguration

Global

Enable

GLOBEN

SIOCF1

Activation

Bit (bit 0)

Index 30h

Device Conﬁguration

Legacy Module

Module

Enable

Module

(Index F0h)

Legacy

Enable

Output

Buffer

1. Wherever the bit is implemented

Winbond Electronics Corp. Advanced PC Product Center

PC8374L Datasheet(PDF) 48 Page - National Semiconductor (TI)

PC8374L Datasheet(HTML) 48 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL