PC8374L datasheet(54/239 Pages) NSC

54 / 239 page

3.0 Device Architecture and Configuration (Continued)

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Revision1.1

3.7.5

SuperI/O Configuration 1 Register (SIOCF1)

Power Well: VDD3

Location:

Index 21h

Type:

Varies per bit

Bit

Name

LOCKMCF

LOCKGCF

Reserved

IOWAIT

SWRST

GLOBEN

Reset

Bit

Type

Description

R/W1S LOCKMCF (Lock Multiplexing Configuration). When set to 1, locks itself, IOWAIT field in SIOCF1

Once set, the bit can be cleared by Hardware reset.

0: R/W bits are enabled for write (default)

1: All bits are RO

R/W1S LOCKGCF (Lock GPIO Pins Configuration). When set to 1,locks the configuration registers of all

GPIO pins (see Section 3.14.2 on page 74) by disabling writes to all their bits (including the LOCKGCF

bit itself). The locked registers include the GPCFG1 (except LOCKCFP bit), GPEVR, GPCFG2 and

GPMODE registers of all GPIO pins. Once set, this bit can be cleared by Hardware reset.

0: R/W bits are enabled for write (default)

1: All bits are RO

5-4

Reserved.

3-2

R/W or

IOWAIT (Number of I/O Wait States). Sets the number of wait states for I/O transactions through the

LPC bus.

Bits

3 2

Number of Wait States

0 0:

0 (default)

01:

10:

11:

R/W

SWRST (Software Reset). When set to 1, triggers the Software reset sequence (see Section 2.2.5 on

page 36), after which it returns to 0. Read always returns 0. The bit is not inﬂuenced by the value of

LOCKMCF.

0: Inactive (default)

1: Trigger the Software reset sequence

R/W or

GLOBEN (Global Device Enable). Enables the disabling of all logical devices by changing a single bit

(to 0). In addition, when the bit is set to 1, it enables the operation of all the logical devices of the

PC8374L, as long as the logical device is itself enabled (see Table 9 on page 39). The behavior of the

different devices is explained in Section 3.3 on page 48.

0: All logical devices in the PC8374L device are forced to be disabled and their resources are released.

1: Enables each PC8374L logical device that is itself enabled (default); see Section 3.3.1 on page 48.

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