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PC8374L Datasheet(PDF) 73 Page - National Semiconductor (TI) |
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PC8374L Datasheet(HTML) 73 Page - National Semiconductor (TI) |
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73 / 239 page  3.0 Device Architecture and Configuration (Continued) Revision 1.1 73 www.national.com 3.14 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION 3.14.1 General Description The GPIO functional block includes 16 pins arranged in two ports: ● Port 0 contains eight GPIOE pins (i.e., GPIO pins with event detection). ● Port 1 contains seven GPIOE pin and one GPIO pin. The two ports (excluding GPIO15) have full event detection capability, enabling them to trigger an IRQ and/or SMI. In addi- tion, through the SWC functional block, they can trigger the SIOPME signal. A configuration option to route GPIOE16 input to GPIOE11 (or GPO11) output is supported. When enabled, GPIOE11 out- puts the data appearing on GPIOE16, ignoring its data output register. For proper operation, GPIOE11 and GPIOE16 need both to be configured correctly. Undefined results otherwise. The runtime registers associated with the ports are arranged in the GPIO address space as shown in Table 29. Each GPIO port with wake-up event detection capability has five runtime registers. The GPIO base address is 32-byte aligned. Address bits 4-0 are used to indicate the register offset. The runtime registers implemented in the PC8374L devices are shown in Table 29. All of these registers are VSB3 powered. Table 29. Runtime Registers in GPIO Address Space Offset Mnemonic Register Name Port Power Well Type SEPDIO = 1 SEPDIO = 0 00h GPDO0 GPIO Data Out 0 0 VSB3 R/W RO 01h GPDI0 GPIO Data In 0 VSB3 RO RO 02h GPEVEN0 GPIO Event Enable 0 VSB3 R/W RO 03h GPEVST0 GPIO Event Status 0 VSB3 R/W1C RO 04h GPDO1 GPIO Data Out 1 1 VSB3 R/W RO 05h GPDI1 GPIO Data In 1 VSB3 RO RO 06h GPEVEN1 GPIO Event Enable 1 VSB3 R/W RO 07h GPEVST1 GPIO Event Status 1 VSB3 R/W1C RO 15h GPDIO0 GPIO Data In/Out 0 0 VSB3 R/W R/W 16h GPDIO1 GPIO Data In/Out 1 1 VSB3 R/W R/W Winbond Electronics Corp. Advanced PC Product Center |
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