PC8374L datasheet(86/239 Pages) NSC

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4.0 System Wake-Up Control (SWC) (Continued)

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Revision1.1

Health Management Events

Health Management events are generated by the Health Management module (HM). These events can create an internal

signal routed to the SWC module, to the HM_STS bit in the GPE1_STS_3 register (see Section 4.4.7 on page 103). A status

bit is updated only when the software writes 1 to it.

For the list of events and routing to SWC module (to the HM_STS bit), see “SCI and SMI Events Routing” in the “Events

Notiﬁcation” section.

4.2.3

Sleep States

The PC8374L identifies the current system sleep state, by decoding the levels of the SLP_S3 and SLP_S5 pins. The levels

of these pins are generated by the system ACPI controller located in an external device. Table 34 shows the decoding of

the logic levels of the SLP_S3 and SLP_S5 pins.

4.2.4

SCI and IRQ Interrupts

The SCI (SIOPME) pin is the Power Management interrupt defined by ACPI.

All external and internal events are exclusively processed by the SWC to generate the Power Management interrupt, SCI.

Each active event sets a status bit in GPE1_STS_0 to GPE1_STS_3 registers (see Sections 4.4.4 to 4.4.7 on page 101).

For each status bit, the SWC holds an enable bit in GPE1_EN_0 to GPE1_EN_3 registers. A set status bit can set PME_STS

bit in GPE1_STS register (see Section 4.4.2 on page 100) only when its related enable bit is set. A set PME_STS bit can

cause the assertion of the SCI interrupt only when PME_EN bit in GPE1_EN register is set (see Section 4.4.3 on page 100).

The SCI interrupt is independent of the system sleep state.

The SIOPME signal can be inverted to generate an active high SCI interrupt. In addition, the output buffer of the SIOPME

pin can be configured as either push-pull or open-drain, to allow sharing with external SCI interrupt sources.

Figure 13 shows SCI generation.

Figure 13. SCI Generation

The SCI interrupt (SIOPME) is routed to the system interrupt (IRQ) by setting the Interrupt Number value, in the Interrupt

Number register, located at index 70h in the SWC Configuration (see Section 3.12.2 on page 70).

Table 34. SLP_S3, SLP_S5 Decoding

SLP_S3

SLP_S5

System Sleep State

S0, S1 or S2

Illegal combination

Enable

GPE1_STS_0-3

Status

Set

GPE1_EN_0-3

Detected Event

(SIOPME)

From Other

Enabled Events

SCI Interrupt

PME_EN

GPE1_STS

PME_STS

Set

GPE1_EN

IRQ

Routing

Control

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PC8374L Datasheet(PDF) 86 Page - National Semiconductor (TI)

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