PC8374L datasheet(85/239 Pages) NSC

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4.0 System Wake-Up Control (SWC) (Continued)

Revision 1.1

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Special Key Sequence mode also enables detection of any single keystroke. To program the Keyboard/Mouse Wake-Up

Detector to wake-up on any single keystroke:

1. Set KBDMODE field in KBDWKCTL register to ‘00’ (see Section 4.3.7 on page 96).

2. Set KBEVCFG field in PS2CTL register to ‘0001’.

3. Program the PS2KEY0 and PS2KEY1 registers to 00h. This forces the detector to ignore the values of incoming data,

thus causing it to detect a keyboard event caused by a single keystroke.

Power Management Mode. In this mode, the PS2KEY0-7 register bank is divided into three groups of registers:

PS2KEY0-2, PS2KEY3-5 and PS2KEY6-7. Each group can be programed with different data bytes, allowing the bytes trans-

mitted by the keyboard to be compared simultaneously with three keystroke sequences. If the bytes transmitted by the key-

board (including Make and Break) are identical to the data bytes in one register group, the related keyboard event is

detected. The detection of Keyboard Event 1 (data in PS2KEY0-2) sets KBD_EVT1_STS bit; the detection of Keyboard

Event 2 (data in PS2KEY3-5) sets KBD_EVT2_STS bit; the detection of Keyboard Event 3 (data in PS2KEY6-7) sets

KBD_EVT3_STS bit. All three status bits are in GPE1_STS_2 register (see Section 4.4.6 on page 102). Each status bit is

cleared only when the software writes 1 to the bit. This mode enables the detection of any sequence of keys.

To program the Keyboard/Mouse Wake-Up Detector to operate in Power Management Keys mode, proceed as follows:

1. Set KBDMODE field in KBDWKCTL register to ‘10’ (see Section 4.3.7 on page 96).

2. Set each event configuration field (EVT1CFG, EVT2CFG and EVT3CFG) in KBDWKCTL register to a value that indi-

cates the desired number of keystroke data bytes (“Make” and “Break” bytes) in the sequence, for each event. For ex-

ample, to detect a sequence of two received bytes, set EVTxCFG to 02h.

3. Program each group of the PS2KEY0-7 registers, in sequential order, with the data bytes of the keys in the sequence

for each event.

Event Generation. Keyboard event detection from KBCLK and KBDAT is enabled, for event generation, tEWIV after VSB3

power is on (see “Wake-Up Inputs at VSB3 Power Switching” on page 236). This prevents the detection of false Keyboard

events during VSB3 power-On transitions.

Usage Hints:

1. After changing the operation mode of the Keyboard/Mouse Wake-Up Detector, clear the KBD_EVT3_STS,

KBD_EVT2_STS, KBD_EVT1_STS, and KBD_ANYK_STS status bits in GPE1_STS_2 register (see Section 4.4.6 on

page 102).

2. If a byte sequence that is a “subset” of the byte sequence of another (“superset”) Power Management key event is used,

the “superset” Power Management key event will never be detected. (The subset sequence has fewer bytes, set by

EVTxCFG fields in KBDWKCTL register, than the superset sequence; however, the bytes contained in the subset se-

quence, as programed in the PS2KEY0-7 registers, are identical to the respective bytes of the superset sequence.)

4.2.2

Internal Events

Keyboard and Mouse IRQ Events

Keyboard and Mouse IRQ events are detected when either the Keyboard IRQ or Mouse IRQ is asserted.

To enable the IRQ of a logical device to generate an IRQ event, the associated Enable bit (bit 4 of the configuration register

at index 70h; see Section 3.2.3 on page 39) must be set to 1. Since the Keyboard Controller (KBC) functional block is pow-

ered by VDD3, a Keyboard or Mouse IRQ event can occur only when VDD3 is present.

An active (level-type) Keyboard IRQ event sets KBD_IRQ_STS status bit; an active Mouse IRQ event sets MS_IRQ_STS

status bit. Both status bits are in GPE1_STS_3 register (see Section 4.4.7 on page 103). A status bit is cleared only when

the software writes 1 to it. If the IRQ event is active when software writes 1 to the status bit, the status bit remains set.

The ROM code used for the Keyboard Controller generates active high Keyboard and Mouse interrupts, which are used by

the SWC module.

Module IRQ Event

A Module IRQ event is detected when one of the Legacy modules (FDC, Parallel Port, Serial Ports 1 and 2. InfraRed Port),

or Health Management module — asserts its IRQ.

To enable the IRQ of a logical device to generate an IRQ event, the associated Enable bit (bit 4 of the configuration register

at index 70h; see Section 3.2.3 on page 39) must be set to 1. This bit is cleared when VDD3 is not present.

MOD_IRQ_STS status bit in GPE1_STS_3 register is set by an IRQ that is asserted by one of the Legacy modules or the

Health Management module (see Section 4.4.7 on page 103). The status bit is cleared only when the software writes 1 to

it. If the Module IRQ event is active when software writes 1 to the status bit, the bit remains set. When VDD3 is not present,

the events from the FDC and Serial Ports 1 and 2 are blocked from the status bit. When VSB3 is not present, the event from

the HM module is blocked from the status bit.

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