PC8374L datasheet(58/239 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision1.1

3.7.10 SuperI/O Revision ID Register (SRID)

This register contains the ID number of the specific family member (Chip ID) and the chip revision number (Chip Rev). The

PC8374L is identified by the value ‘000’. The Chip Rev is incremented on each revision.

Power Well: VSB3

Location:

Index 27h

Type:

R/W or

SER1DIS (Serial Port 1 Disable). When set to 1, forces the Serial Port 1 module to be disabled (and

its resources released) regardless of the actual setting of its Activation bit (index 30).

0: Enabled or Disabled, according to Activation bit (default)

1: Disabled

R/W or

SER2DIS (Serial Port 2 Disable). When set to 1, forces the Serial Port 2 with InfraRed Port module to

be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30).

0: Enabled or Disabled, according to Activation bit (default)

1: Disabled

R/W or

PARPDIS (Parallel Port Disable). When set to 1, forces the Parallel Port module to be disabled (and

its resources released) regardless of the actual setting of its Activation bit (index 30).

0: Enabled or Disabled, according to Activation bit (default)

1: Disabled

R/W or

FDCDIS (Floppy Disk Controller Disable). When set to 1, forces the Floppy Disk Controller module to

be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30).

0: Enabled or Disabled, according to Activation bit (default)

1: Disabled

Bit

76543210

Name

Chip ID

Chip Rev

Reset

XXXXX

Bit

Description

7-5

Chip ID. Identifies a specific device of a family.

4-0

Chip Rev. Identifies the device revision.

Bit

Type

Description

Winbond Electronics Corp. Advanced PC Product Center

PC8374L Datasheet(PDF) 58 Page - National Semiconductor (TI)

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