PC8374L datasheet(36/239 Pages) NSC

36 / 239 page

2.0 Power, Reset and Clocks (Continued)

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Revision1.1

Hardware reset performs the following actions:

• Resets all lock bits in configuration registers, Health Management and SWC

• Sets up the pull-up or pull-down option and the default source for the V

DD3-powered multiplexed output pins

• Executes all the actions performed by the Software reset (see Section 2.2.5)

2.2.5

Software Reset

The Software reset is triggered by the host setting SWRST bit in SIOCF1 register (see Section 3.7.5 on page 54) via the

LPC interface. The Host Software reset performs the following actions:

• Loads default values to the V

DD3-powered unlocked bits in the Configuration Control.

• Loads default values to the V

SB3-powered unlocked GPIO Configuration and Data bits for those GPIO ports with

VDDLOAD = 1. VDDLOAD bit is not affected.

• Resets all the V

DD3-powered logical devices.

• Loads default values to all the V

DD3-powered module registers, unless explicitly specified otherwise.

2.3 CLOCK DOMAINS

Table 7 shows the PC8374L clock domains.

The LPC and 48 MHz clock domains, and the modules using them, are supplied by the Main power plane. Therefore, these

clock domains are active only when the VDD3 power supply is on.

The Standby and SW_360 clock domains are sourced by the on-chip Clock Generator. The clock domains become active

a certain time after first VDD3 power-up following VSB3 power-up, and they remain active as long as VSB3 exists.

The 32 KHz clock domain is sourced by the on-chip Clock Generator, which is supplied by the Standby power plane. The

32 KHz clock domain is active when the VSB3 power supply is on.

2.3.1

LPC Domain

The LPC clock signal at the PCI_CLK pin must become valid (to the extent specified in “PCI_CLK and PCI_RESET” on

page 224) before the end of the VDD Power-Up reset (see Section 2.2.3).

2.3.2

48 MHz Domain

The 48 MHz clock domain is sourced by the on-chip Clock Generator. The software must wait for CKVALID bit (see Section 3.7.11

on page 59) to be set before it enables the Legacy functions (Serial Ports, InfraRed Port, Parallel Port, FDC, KBC).

2.3.3

Standby Domain

The on-chip Clock Generator is the source of the Standby clock domain and all the other clock domains derived from it:

SW_360 and 32 KHz.

Note that the Health Management is functional only after first VDD3 power-up following VSB3 power-up. The SWC, GPIO and

Glue are functional on VSB3 power up.

The Standby clock is scaled-down by a fixed divider to generate the SW_360 clock domain used by the Health Management

module. In addition, the Standby clock is supplied directly to the Health Management module for the generation of PWM

output signals in the high frequency range. The 32 KHz clock domain is also derived from a scaled-down divider of the Stand-

by clock.

Table 7. Clock Domains of the PC8374L

Clock

Domain

Frequency

Power

Plane

Source

Usage

LPC

Up to 33 MHz

VDD3

LPC clock input (PCI_CLK)

LPC bus Interface and Conﬁguration Registers

48 MHz

VDD3

On-Chip Clock Generator

Legacy functions (Serial Ports, InfraRed Port,

Parallel Port, FDC, KBC)

Standby

48 MHz

VSB3

On-Chip Clock Generator

Health Management Module

SW_360

360 KHz

VSB3

On-Chip Clock Generator

Health Management Module

32 KHz

32.768 KHz

VSB3

On-Chip Clock Generator

SWC, GPIO and Glue Functions

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PC8374L Datasheet(PDF) 36 Page - National Semiconductor (TI)

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