PC8374L datasheet(89/239 Pages) NSC

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4.0 System Wake-Up Control (SWC) (Continued)

Revision 1.1

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4.2.6

Special Power Management Functions

Last Power State

Last Power State function saves the system power state when an AC power failure occurs.

When either the VDD3 or VSB3 power supply falls below the minimum limit, the SWC samples the value of the SLP_S3 signal.

If SLP_S3 is sampled low, this indicates an orderly shutdown of the Main supply through the S3-S5 sleep states; however,

if SLP_S3 is sampled high, this indicates a Power Fail condition, caused either by turning off the mechanical switch (G2

state) or by an AC power failure. The sampled value is powered by the VBAT backup supply, which preserves its value

throughout the Power Fail condition when both VDD3 and VSB3 supplies are off (see Section 2.1.2 on page 32) and until AC

power returns. When the system exits Power Fail (i.e., when VSB3 power is back on), this read-only bit serves as a snapshot

of the system state before the power was turned off.

The level of the SLP_S3 signal is sampled in LAST_PWR_STATE read-only bit in SWC_CTL register (see Section 4.3.3 on

page 92).

In case of a power failure, both VDD and VSB power supplies fall simultaneously. Therefore, the power failure is detected

either by VDD3 falling below VDD3OFF, or by VSB3 falling below VSB3OFF, whichever occurs ﬁrst.

The LAST_PWR_STATE bit is reset to 0 at VBAT power-up (see Section 2.2.1 on page 35).

Backup Battery Status

This function detects the status of the backup battery (VBAT). When the battery voltage is below the specification (VBAT <

VBATLOW), GOOD_BAT and LAST_PWR_STATE bits in SWC_CTL register (see Section 4.3.3 on page 92) are reset. In this

case, the value of LAST_PWR_STATE bit is incorrect and must be ignored.

If the battery voltage is within specified limits (VBAT >VBATLOW), GOOD_BAT bit is set when either the VDD3 or the VSB3

power supply falls below the minimum limit.

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PC8374L Datasheet(PDF) 89 Page - National Semiconductor (TI)