AD4697 datasheet(31/107 Pages) AD

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Data Sheet

AD4697/AD4698

THEORY OF OPERATION

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Rev. 0 | 31 of 107

When an even numbered input is paired with its corresponding

odd numbered input, selecting the odd numbered input through

any of the channel sequencing modes is functionally identical to

selecting the even numbered input. The even numbered input is

always connected to ADCIN+, the odd numbered input is always

connected to ADCIN−, and only the settings in the even numbered

input CONFIG_INn register are applied. It is recommended to only

include the even numbered input in the channel sequence when the

input is assigned as part of a channel pair.

When the standard sequencer is enabled, the pin pairing assign-

ment settings are the same for all eight analog inputs and are set

by the IN_PAIR bit field in the CONFIG_IN0 register. When the

advanced sequencer, two-cycle command mode, or single-cycle

command mode is enabled, the pin pairing assignment settings are

independent for all eight analog inputs and are set by the IN_PAIR

bit field in the corresponding CONFIG_INn register for each input.

The polarity mode settings for each analog input are always set

by the IN_MODE bit in the corresponding CONFIG_INn registers,

regardless of the channel sequencing mode.

Note that pseudobipolar mode is not available for channels with the

REFGND pin pairing assignment selected. If a channel pin pairing

assignment is configured as REFGND, the state of the IN_PAIR bit

field is ignored.

Figure 68. INx Paired with REFGND

Figure 69. INx Paired with COM

Figure 70. Even-Channel and Odd-Channel Paired

Analog Input High-Z Mode

To achieve optimal data sheet performance from traditional high

resolution multiplexed SAR ADCs, system designers must often

include dedicated, high bandwidth, low noise ADC driver amplifiers

between the analog signal conditioning circuitry and the ADC inputs

to settle the voltage kickback that occurs at the analog inputs

between conversions. The AD4697/AD4698 analog input high-Z

mode simplifies the design requirements of the AFE circuitry that

drives the analog inputs and facilitates the design of small footprint,

high channel density, precision multiplexed SAR ADC signal chains.

Analog input high-Z mode significantly reduces the magnitude of

the voltage kickback that occurs at the analog inputs when the

ADC and multiplexer switches reconnect at the start of the ADC

acquisition phase (see the Signal Settling Requirements section).

Figure 21 shows the voltage kickback that occurs on an analog

input driven to 5 V after switching from another analog input driven

to 0 V with analog input high-Z mode disabled and enabled.

The reduction in the voltage kickback increases the effective input

impedance of the AD4697/AD4698 analog inputs and reduces the

bandwidth requirements of the AFE circuitry to achieve desired

settling accuracy and performance. The relaxed bandwidth require-

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