AD4697 datasheet(35/107 Pages) AD

35 / 107 page

Data Sheet

AD4697/AD4698

THEORY OF OPERATION

analog.com

Rev. 0 | 35 of 107

REF input without impacting performance (see the Reference Input

High-Z Mode section). The internal reference buffer (available in the

WLCSP option only) also provides a true buffered reference input

(see the Internal Reference Buffer section).

The average REF input current scales with sample rate (see

Table 1 and Figure 40).

Reference Input High-Z Mode

When enabled, reference input high-Z mode reduces the average

REF current by approximately 95% from 320 µA/MSPS to

11 µA/MSPS (see Table 1). The reduction in REF current allows

the AD4697/AD4698 to tolerate larger series resistance between

the reference source and the REF input without compromising per-

formance. Therefore, reference input high-Z mode allows voltage

references with higher load regulation specifications to directly drive

the REF input without the need for a dedicated reference buffer.

The REF input requires a reference decoupling capacitor (CREF).

When reference input high-Z mode is disabled, CREF must be 10 µF

or larger. When reference input high-Z mode is enabled, CREF can

be as small as 1 µF.

See the Reference Circuitry Design section for more reference

circuit design recommendations.

To enable and disable reference input high-Z mode, set the value

of the REFHIZ_EN bit in the REF_CTRL register. Reference input

high-Z mode is enabled by default.

Analog input high-Z mode must be enabled when reference input

high-Z mode is enabled. If any analog input channels are config-

ured with analog input high-Z mode disabled, reference input high-Z

mode must also be disabled.

Internal Reference Buffer

The internal reference buffer (available only in the WLCSP option of

the AD4698) provides a true buffered reference input (REFIN). The

internal reference buffer is useful in applications using unbuffered,

low power, reference sources or where multiple devices share a

common reference source. As described in the Reference Circuit

Design for Internal Reference Buffer section, an RC low-pass filter

with a very low cutoff frequency can be implemented at the internal

reference buffer input to significantly reduce wideband noise from

the reference source.

When the internal reference buffer is enabled, the maximum allowa-

ble VREF is AVDD – 0.3 V (see Table 1).

When not using the internal reference buffer, REFIN must be tied to

REF.

When the internal reference buffer is enabled, the AD4698 draws

approximately 450 μA more current through the AVDD supply;

however, this is still typically less additional supply current when

compared to a dedicated external reference buffer that is traditional-

ly required to drive the reference input of a SAR ADC.

Table 1 shows power consumption with the internal reference buffer

disabled and enabled.

Figure 74 shows a simplified diagram of the AD4698 internal refer-

ence buffer. The internal reference buffer is enabled by setting the

REFBUF_EN bit in the REF_CTRL register to 1. The reference in-

put high-Z mode must be enabled when using the internal reference

buffer (REFHIZ_EN = 1). The internal reference buffer is disabled

by default.

When the internal reference buffer is disabled, setting the RE-

FBUF_BP bit in the REF_CTRL register bypasses the internal refer-

ence buffer by internally connecting the REFIN and REF pins (via

SWBP). When the internal reference buffer is enabled (REFBUF_EN

= 1), the value of the REFBUF_BP bit is ignored, and SWBP is

always open. Do not operate the AD4698 in conversion mode while

the REFBUF_BP bit is set to 1.

The internal reference buffer turn-on time specification (tREFBUF

in Table 1) is the delay between enabling the internal reference

buffer and the REF pin voltage transitioning from 0 V to VREF

within 0.01%. tREFBUF is proportional to CREF. Figure 44 shows

the internal reference buffer driving VREF vs. time and CREF. The

internal reference buffer includes a boost mode, which reduces the

internal reference buffer turn-on time when it is enabled by increas-

ing the internal reference buffer output current (see the Optimizing

Reference Buffer Startup section). Set the REFBUF_BOOST bit in

the REF_CTRL register to 1 to enable reference buffer boost mode.

Reference buffer boost mode is disabled by default.

Figure 74. Internal Reference Buffer Simplified Schematic

POWER SUPPLIES

The AD4697/AD4698 have three power supply pins: an analog

supply (AVDD), an ADC core supply (VDD), and a digital input/out-

put interface supply (VIO). The AD4697/AD4698 also include an

internal LDO that can be used to provide the VDD rail with a

wider variety of supply voltages (or in single-supply systems by

tying LDO_IN to AVDD). Table 1 shows the specified power supply

voltage requirements.

AVDD can range from 3.15 V to 5.5 V and powers the AFE features

of the AD4697/AD4698, including the multiplexer, analog input

high-Z mode and reference input high-Z mode circuitry, and the

internal reference buffer (WLCSP option only). When the internal

AD4697 Datasheet(PDF) 35 Page - Analog Devices

AD4697 Datasheet(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL