AD4697 datasheet(42/107 Pages) AD

42 / 107 page

Data Sheet

AD4697/AD4698

THEORY OF OPERATION

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Rev. 0 | 42 of 107

When the advanced sequencer is enabled, the configuration set-

tings for each channel are set with the corresponding CONFIG_INn

configuration options, analog input high-Z mode enable settings,

OSR settings, and threshold detection enable settings. Configure

each CONFIG_INn register before entering conversion mode and

initiating conversions.

The multiplexer does not advance to the next channel in the

sequence until the required number of conversions dictated by the

selected channel OSR setting is complete. When the OSR of a

channel in the sequence is set to a value other than 1 (when the

OSR_SET bit field in the corresponding CONFIG_INn register is

not set to 0x0), the advanced sequencer does not advance to the

next channel in the sequence, and the busy indicator does not

transition low until the required number of conversions is complete.

For example, if the OSR is set to 16, 16 CNV rising edges are

required before the conversion result is ready, and the multiplexer

selects the next channel in the sequence. Figure 78 shows an

example timing diagram where OSR for IN0 is set to N. See the

Oversampling and Decimation section for more information.

When the advanced sequencer is enabled, the channel sequence

can be configured to achieve different effective sample rates for

each channel. See the Effective Channel Sample Rate section for

more information.

Two-Cycle Command Mode

Two-cycle command mode allows the digital host system to man-

ually control the next channel in the sequence on-the-fly and ena-

bles dynamic channel sequencing without interrupting conversions.

In two-cycle command mode, the channel sequence is determined

by 5-bit commands transmitted from the digital host during conver-

sion result readback frames. The 5-bit commands are clocked in

on the SDI on the first five SCK rising edges in the frame and

latched into memory on the sixth SCK falling edge in the frame. If

a valid channel command is received, the conversion result for that

channel is available after two conversion periods. Figure 79 shows

the relative timing between the 5-bit commands (represented by

CMD) and the corresponding acquisition phase, conversion phase,

and conversion result readback in two-cycle command mode.

Two-cycle command mode maximizes the acquisition time for all

channels because the 5-bit channel commands are latched in

before the multiplexer switches select the corresponding channel

and begin the ADC acquisition phase.

Table 18 shows the valid commands for selecting IN0 to IN7 or the

temperature sensor. Commands other than those listed in Table 18

are treated as no operation (NOOP) commands and result in the

multiplexer repeating the previous channel.

When two-cycle command mode is enabled, the first analog input

channel selected is the one specified in the AS_SLOT0 register.

The channel only updates when a valid command code is received.

To enable two-cycle command mode, set the STD_SEQ_EN bit

to 0, set the NUM_SLOTS_AS bit field to 0x00, and set the

CYC_CTRL bit to 0 (see Table 15).

While the AD4697/AD4698 are in register configuration mode when

the STD_SEQ_EN bit in the SEQ_CTRL register is set to 0, the

multiplexer automatically connects the channel specified in the

AS_SLOT0 register to the ADC core inputs, which allows the ADC

to acquire the signal on that channel even before the device enters

conversion mode.

When two-cycle command mode is enabled, the configuration

settings for each channel are set with the corresponding CON-

FIG_INn register. Therefore, all analog inputs can have different

channel configuration options, analog input high-Z mode enable

settings, and threshold detection enable settings. Configure each

CONFIG_INn register before entering conversion mode and initiat-

ing conversions.

Oversampling is not supported when two-cycle command mode is

enabled. Set the OSR for all analog inputs to 1 before entering

conversion mode with two-cycle command mode enabled (see the

Oversampling and Decimation section).

Single-Cycle Command Mode

Single-cycle command mode allows the digital host system to

manually control the next channel in the sequence on-the-fly and

enables dynamic channel sequencing without interrupting conver-

sions.

In single-cycle command mode, the channel sequence is deter-

mined by 5-bit commands transmitted from the digital host dur-

ing conversion result readback frames. The 5-bit commands are

clocked in on the SDI on the first five SCK rising edges in the frame

and latched into memory on the sixth SCK falling edge in the frame.

If a valid channel command is received, the conversion result for

that channel is available in only one conversion period. Figure 80

shows the relative timing between the 5-bit commands (represented

by CMD) and the corresponding acquisition phase, conversion

phase, and conversion result readback in single-cycle command

mode.

Single-cycle command mode minimizes the latency between the

5-bit channel commands and the corresponding ADC data because

the multiplexer switches select the specified channel immediately

after the 5-bit command latches into memory. As a result, the ac-

quisition time depends on how quickly the digital host can complete

the write of the 5-bit command. Figure 100 shows a conversion

mode timing diagram with single-cycle command mode enabled,

and Table 2 lists the relevant timing specifications. The tACQ in

single-cycle command mode is a function of tCYC and the SCK

period (tSCK), and is calculated with the following expression:

tACQ=tCYC− 5.5×tSCK

(7)

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