 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD4697 Datasheet(PDF) 93 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD4697 Datasheet(HTML) 93 Page - Analog Devices |
|
|
93 / 107 page  Data Sheet AD4697/AD4698 REGISTER INFORMATION analog.com Rev. 0 | 93 of 107 SPI Configuration C Register Address: 0x0010, Reset: 0x23, Name: SPI_CONFIG_C Table 39. Bit Descriptions for SPI_CONFIG_C Bits Bit Name Description Reset Access [7:6] CRC_EN CRC Enable Field. This field enables the CRC when set to 0x1 (if CRC_EN_N is also set to 0x2). This field disables the CRC when set to a value other than 0x1 (see the Checksum Protection section). 0x0 R/W 0: disables CRC. 1: enables CRC if CRC_EN_N = 0x2. 5 MB_STRICT Multibyte Access Control Bit. This bit sets the SPI transaction requirements for multibyte registers (see the Multibyte Register Access section). 0x1 R/W 0: individual bytes in multibyte registers are read from or written to in individual data phases. 1: all bytes in multibyte registers are read from or written to in a single data phase. [4:2] RESERVED Reserved. 0x0 R [1:0] CRC_EN_N Inverted CRC Enable Field. This field enables the CRC when set to 0x2 (if CRC_EN is also set to 0x1). This field disables the CRC when set to a value other than 0x2 (see the Checksum Protection section). 0x3 R/W Interface Status Register Address: 0x0011, Reset: 0x00, Name: SPI_STATUS Table 40. Bit Descriptions for SPI_STATUS Bits Bit Name Description Reset Access 7 NOT_RDY_ERROR Interface Not Ready Error Flag. This bit is set to 1 when the digital host initiates an SPI transaction before the AD4697/AD4698 interface is ready to respond, for example, before a device reset is complete. 0x0 R/W1C [6:5] RESERVED Reserved. 0x0 R 4 SCK_ERROR SPI Clock Count Error Flag. This bit is set to 1 when an incorrect number of serial clock edges is received in an SPI read or write transaction, for example, if the SPI frame ends in the middle of a data phase. 0x0 R/W 3 CRC_ERROR CRC Error Flag. This bit is set to 1 when the AD4697/AD4698 receives a checksum that does not match its expected value (see the Checksum Protection section). This error flag is only active when the CRC is enabled. 0x0 R/W1C 2 WRITE_INVALID Invalid Write Error Flag. This bit is set to 1 when the digital host attempts an SPI write to a register that contains exclusively read only bits. 0x0 R/W1C 1 MB_ERROR Multibyte Register Access Error Flag. This bit is set to 1 when an SPI transaction does not access all bytes of a multibyte register. This error flag is only active when the MB_STRICT bit is set to 1. 0x0 R/W1C |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
