AD4697 datasheet(50/107 Pages) AD

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Data Sheet

AD4697/AD4698

DIGITAL INTERFACE

analog.com

Rev. 0 | 50 of 107

The CRC is enabled with the CRC_EN and CRC_EN_N bit fields

in the SPI_CONFIG_C register. To enable the CRC, CRC_EN must

be set to 0x1 and CRC_EN_N must be set to 0x2. CRC is disabled

for all other combinations of CRC_EN and CRC_EN_N.

The AD4697/AD4698 expect checksums to be included in each

SPI transaction immediately after the CRC is enabled. Write to the

SPI_CONFIG_C register to enable the CRC before writing to any

other registers, then read the SPI_CONFIG_C register assuming

that the CRC has been enabled. If the host receives the correct

state of the CRC_EN and CRC_EN_N bit fields and a valid check-

sum, the CRC is enabled, and the host can begin configuring the

remaining configuration registers.

Use the following CRC polynomial to calculate the checksums:

x8+x2+x+1

(8)

The CRC calculation is seeded by a non-zero value to detect if the

data lines are stuck low. Table 16 shows the data and seed values

for each possible type of SPI transaction.

In single instruction mode, the seed for all CRCs is 0xA5. In stream-

ing mode, the seed for the first CRC in the frame is also 0xA5, but

the seed for the remaining CRCs in the frame is the least significant

byte of the register address being accessed. If MB_STRICT is set

to 1 and a multibyte register is accessed, the register address used

for the seed depends on the selected address direction option.

The address of the most significant byte is used with descending

address, and the address of the least significant byte is used with

ascending address. For example, in both Figure 86 and Figure 87,

the second data phase includes data from the UPPER_IN0 register,

but the seed used for the checksum is 0x41 with the descending

address option (Figure 86) and 0x40 with the ascending address

option (Figure 87).

Table 16. CRC Input Values for SPI Modes and Transactions

SPI Transaction Type

Single Instruction Mode or First CRC with Streaming Mode

Subsequent CRCs with Streaming Mode

Write

SDI

SPI data = instruction phase bits, data phase bits

SPI data = data phase bits

Seed = 0xA5

Seed = least significant byte of current register address

SDO

SPI data = instruction phase bits, data phase bits

SPI data = data phase bits

Seed = 0xA5

Seed = least significant byte of current register address

Read

SDI

SPI data = instruction phase bits, padding bits

Not applicable

Seed = 0xA5

SDO

SPI data = instruction phase bits, data phase bits

SPI data = data phase bits

Seed = 0xA5

Seed = least significant byte of current register address

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