AD4697 datasheet(53/107 Pages) AD

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Data Sheet

AD4697/AD4698

DIGITAL INTERFACE

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Rev. 0 | 53 of 107

Serial Data Output Modes

The AD4697/AD4698 digital interface allows clocking out ADC

data on more than one serial data output, which reduces the

number of SCK periods required to access the full ADC result and

allows slower SCK frequencies. The three serial data output modes

include single-SDO mode, dual-SDO mode, and quad-SDO mode.

In single-SDO mode, the ADC results are only shifted out on SDO.

In dual-SDO mode and quad-SDO mode, ADC results are shifted

out on SDO and general-purpose pins in parallel.

Table 19 shows the pins used for each serial data output signal

for each serial data output mode. Table 21 and Table 22 show the

formatting of the conversion results for all combinations of serial

data output modes, status bits, and OSR options. The values of

the blank cells in Table 21, Table 22, and Table 23 depend on

the setting of SDO_STATE, as described in the Conversion Mode

Timing Diagrams section.

The serial data output modes only apply when the device is in

conversion mode. In register configuration mode, register read data

is always shifted out serially on SDO only.

The SDO_MODE bit field in the setup register determines which

serial data output mode is selected. Table 20 shows the values

of SDO_MODE and the corresponding serial data output modes.

Quad-SDO mode is only available in the WLCSP option of the

AD4698.

Table 19. Serial Data Output Mode Pin Assignments

Mode

Signal

LFCSP Pins

WLCSP Pins

Single-SDO Mode

SDO0

SDO

Dual-SDO Mode

SDO1

BSY_ALT_GP0

GP1

SDO0

SDO

Quad-SDO Mode

SDO3

Not applicable

GP3

SDO2

Not applicable

GP2

SDO1

Not applicable

GP1

SDO0

Not applicable

SDO

Table 20. SDO_MODE Values vs. Serial Data Output Mode

SDO_MODE

LFCSP Mode

WLCSP Mode

0x0

Single-SDO

0x1

Dual-SDO

0x2

Single-SDO

Quad-SDO

0x3

Single-SDO

Table 21. Single-SDO Mode Data Output Format

OSR Setting

Status

Bits

Signal

SCK Falling Edge Number

… 15

Disabled

SDO0

D15

D14

D13

… D1

Disabled

SDO0

D16

D15

D14

… D2

Disabled

SDO0

D17

D16

D15

… D3

Disabled

SDO0

D18

D17

D16

… D4

Enabled

SDO0

D15

D14

D15

… D1

OV_ALT

INX, Bit 3

INX, Bit 2

INX, Bit 1

INX, Bit 0

Enabled

SDO0

D16

D15

D16

… D2

OV_ALT

INX, Bit 3

INX, Bit 2

INX, Bit 1

INX, Bit 0

Enabled

SDO0

D17

D16

D17

… D3

OV_ALT

INX, Bit 3

INX, Bit 2

INX, Bit 1

INX, Bit 0

Enabled

SDO0

D18

D17

D16

… D4

OV_ALT

INX, Bit 3

INX, Bit 2

INX, Bit 1

INX, Bit 0

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