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AD4697 Datasheet(PDF) 99 Page - Analog Devices |
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AD4697 Datasheet(HTML) 99 Page - Analog Devices |
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99 / 107 page ![]() Data Sheet AD4697/AD4698 REGISTER INFORMATION analog.com Rev. 0 | 99 of 107 Table 46. Bit Descriptions for REF_CTRL Bits Bit Name Description Reset Access 0: reference buffer boost mode disabled. 1: reference buffer boost mode enabled. [4:2] VREF_SET Reference Input Range Control. This field configures the device to optimize performance based on the reference voltage in use. This field must be programmed to match the VREF applied to the REF pin (see the Voltage Reference Input section). 0x4 R/W 0x0: 2.4 V ≤ VREF ≤ 2.75 V. 0x1: 2.75 V < VREF ≤ 3.25 V. 0x2: 3.25 V < VREF ≤ 3.75 V. 0x3: 3.75 V < VREF ≤ 4.50 V. 0x4: 4.5 V < VREF ≤ 5.10 V. 1 REFHIZ_EN Reference Input High-Z Mode Enable Bit. This bit enables or disables reference input high-Z mode (see the Reference Input High-Z Mode section). 0x1 R/W 0: disable reference input high-Z mode. 1: enable reference input high-Z mode. 0 REFBUF_EN Reference Buffer Enable Bit. Enables or disables the reference buffer. Setting REFBUF_EN to 1 also forces the reference buffer bypass switch to open (see the Internal Reference Buffer section). This bit is only active on the WLCSP option. Setting this bit on the LFCSP option has no effect. 0x0 R/W 0: disables the internal reference buffer. 1: enables the internal reference buffer. Sequencer Control Register Address: 0x0022, Reset: 0x80, Name: SEQ_CTRL Table 47. Bit Descriptions for SEQ_CTRL Bits Bit Name Description Reset Access 7 STD_SEQ_EN Standard Sequencer Enable Bit. This bit enables or disables the standard sequencer (see the Channel Sequencing Modes section). 0x1 R/W 0: standard sequencer disabled. 1: standard sequencer enabled. [6:0] NUM_SLOTS_AS Number of Advanced Sequencer Slots Field. This field determines the number of slots in a sequence when the advanced sequencer is enabled. The number of slots is equal to NUM_SLOTS_AS + 1. This field must be set to 0x00 to enable two-cycle command mode or single-cycle command mode (see the Channel Sequencing Modes section). 0x0 R/W |
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