AD4697 datasheet(37/107 Pages) AD

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Data Sheet

AD4697/AD4698

THEORY OF OPERATION

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shows the relative timing of the CNV signal and the availability of

the oversampled result. Consider the OSR of each channel when

designing the channel sequence to achieve the desired certain

effective sample rates for each channel (see the Effective Channel

Sample Rate section).

The OSR is configured via the OSR_SET bit fields in the CON-

FIG_INn registers (see Table 54).

When the standard sequencer is enabled, the OSR for all analog

input channels is the same and is set by the OSR_SET bit fields

in the CONFIG_IN0 register. When the advanced sequencer is

enabled, each of the eight analog input channels can be configured

with different OSR settings with the OSR_SET bit fields in the

corresponding CONFIG_INn registers.

Oversampling is not supported in two-cycle command mode or

single-cycle command mode. Set the OSR_SET bit fields for all

active channels to 0x0 when using two-cycle command mode or

single-cycle command mode.

When autocycle mode is enabled, the conversion signal is generat-

ed internally by the AD4697/AD4698, and the oversampling engine

continues to wait for OSR conversion periods before generating an

output result.

OFFSET AND GAIN CORRECTION

The AD4697/AD4698 include offset and gain error correction func-

tionality to correct for first-order nonidealities in a full AFE signal

chain. Offset and gain error correction digitally adjusts the offset

and gain of the overall ADC transfer function (see the Transfer

Function section).

The final output code is calculated with the following expression:

OUT= IN+B ×M

(5)

where:

OUT is the final output code result.

IN is the result generated by the ADC (after oversampling).

B is the offset correction value.

M is the gain correction value.

The gain correction value (M) for each analog input is set with the

gain bit field in the corresponding GAIN_INn register. The gain bit

field is 16 bits wide and is in straight binary format. The range of

gain correction values is 0 to 1.99997 and is calculated with the

following expression:

M=Gain÷215

(6)

where GAIN is the value written to the gain bit field.

The offset correction value (B) for each analog input is set with

the offset bit field in the corresponding OFFSET_INn register. The

OFFSET bit field is 16 bits wide and is in twos complement format

to enable positive and negative offset correction. The range of

offset correction values is ±FSR/8 for all OSR options, which means

the MSB of the offset bit field always corresponds to the (MSB –

3) bit of the ADC result. For example, when the OSR for a given

analog input channel is 1, the offset correction value is equal to

OFFSET, Bits[15:3], and when the OSR is 64, the offset correction

value is OFFSET, Bits[15:0]. Table 14 shows the offset correction

value for each OSR option.

Offset and gain correction are always enabled for all analog input

channels. When the OFFSET field for a given analog input is set

to 0x0000, the offset correction value is 0 and is equivalent to

applying no offset correction. When the GAIN bit field for a given

analog input is set to 0x8000, the gain correction value is 1 and is

equivalent to applying no gain correction.

Table 14. Oversample Ratio vs. Offset Correction Value

Oversample Ratio

Offset Correction Value (B)

OFFSET, Bits[15:3]

OFFSET, Bits[15:2]

OFFSET, Bits[15:1]

OFFSET, Bits[15:0]

THRESHOLD DETECTION AND ALERT

INDICATORS

The AD4697/AD4698 include a threshold detection feature with

alert indicators that notify the digital host system when a conversion

result violates user defined upper and lower limits.

The TD_EN bit in the CONFIG_INn registers enables or disables

threshold detection for the corresponding analog input. When the

standard sequencer is enabled, threshold detection is enabled

or disabled for all analog inputs with the TD_EN bit in the CON-

FIG_IN0 register. When the advanced sequencer, two-cycle com-

mand mode, or single-cycle command mode is enabled, threshold

detection is enabled or disabled for each analog input independent-

ly with the TD_EN bit in each of the corresponding CONFIG_INn

registers.

When threshold detection is enabled for a given analog input, the

ADC results generated for that analog input are compared against

an upper threshold value and lower threshold value. Upper and

lower threshold values can be independently assigned for each of

the eight analog inputs. The upper and lower threshold values for

the eight analog inputs are set with the upper and lower bit fields in

the UPPER_INn and LOWER_INn registers. The upper and lower

bit fields are 12 bits wide and correspond to the 12 MSBs of the

ADC results for all OSR options. For example, setting the upper bit

field to 0xFFF corresponds to an upper threshold value of 0xFFF0

when the OSR of that channel is 1, and 0x7FF80 when the OSR of

that channel is 64 (see the Oversampling and Decimation section).

When an analog input is configured in unipolar mode, the corre-

sponding upper and lower bit fields are in straight binary format.

When an analog input is configured in pseudobipolar mode, the

corresponding upper and lower bit fields are in twos complement

format.

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