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PIC10F222IP Datasheet(PDF) 34 Page - Microchip Technology

Part # PIC10F222IP
Description  6-Pin, 8-Bit Flash Microcontrollers
PDF  78 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC10F222IP Datasheet(HTML) 34 Page - Microchip Technology

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PIC10F220/222
DS41270B-page 32
Preliminary
© 2006 Microchip Technology Inc.
7.9
A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 7-1. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 7-1.
The maximum recommended impedance for analog
sources is 10 k
Ω. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 7-1 may be used. This equation
assumes that 1/2 LSb error is used (256 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
EQUATION 7-1:
ACQUISITION TIME EXAMPLE
FIGURE 7-1:
ANALOG INPUT MODEL
TACQ
Amplifier Settling Time
Hold Capacitor Charging Time
Temperature Coefficient
++
=
TAMP
TC
TCOFF
++
=
2µs
TC
Temperature - 25°C
() 0.05µs/°C
()
[]
++
=
TC
CHOLD RIC
RSS
RS
++
() ln(1/512)
–
=
25
pF 1k
Ω 7kΩ 10kΩ
++
()
–
ln(0.00196)
=
2.81
=
µs
TACQ
2µS
2.81µS
50°C- 25°C
() 0.05µS/°C
()
[]
++
=
6.06u
s
=
Solving for TC:
Therefore:
Temperature
50°C and external impedance of 10k
Ω 5.0V VDD
=
Assumptions:
Note 1: The charge holding capacitor (CHOLD) is not discharged after each conversion.
2: The maximum recommended impedance for analog sources is 10 k
Ω. This is required to meet the pin
leakage specification.
CPIN
VA
Rs
ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V
I LEAKAGE
RIC
≤ 1k
Sampling
Switch
SS
Rss
CHOLD = 25 pF
VSS/VREF-
6V
Sampling Switch
5V
4V
3V
2V
567 8 9 10 11
(k
Ω)
VDD
± 500 nA
Legend: CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
various junctions
RSS



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