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AX5043 Datasheet(PDF) 14 Page - ON Semiconductor

Part # AX5043
Description  Advanced High Performance ASK and FSK Narrow-band Transceiver for 27-1050 MHz Range
PDF  47 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

AX5043 Datasheet(HTML) 14 Page - ON Semiconductor

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AX5043
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14
Table 13. RECEIVER AND TRANSMITTER SETTLING PHASES
Symbol
Description
Condition
Min
Typ
Max
Units
Txtal
XTAL settling time
Powermodes:
POWERDOWN to STANDBY
Note that Txtal depends on the specific
crystal used.
0.5
ms
Tsynth
Synthesizer settling time
Powermodes:
STANDBY to SYNTHTX or SYNTHRX
40
ms
Ttx
TX settling time
Powermodes:
SYNTHTX to FULLTX
Ttx is the time used for power ramping, this
can be programmed to be 1 x tbit, 2 x tbit,
4 x tbit or 8 x tbit.
Notes 1, 2
0
1 x tbit
8 x tbit
ms
Trx_init
RX initialization time
150
ms
Trx_rssi
RX RSSI acquisition time
(after Trx_init)
Powermodes:
SYNTHRX to FULLRX
Modulation (G)FSK
Notes 1, 2
80 +
3 x tbit
ms
Trx_preambl-
e
RX signal acquisition time to
valid data RX at full sensitivi-
ty/selectivity
(after Trx_init)
9 x tbit
1. tbit depends on the datarate, e.g. for 10 kbps tbit = 100 ms
2. In wire mode there is a processing delay of typically 6 x tbit between antenna and DCLK/DATA pins
Table 14. OVERALL STATE TRANSITION TIMES
Symbol
Description
Condition
Min
Typ
Max
Units
Ttx_on
TX startup time
Powermodes:
STANDBY to FULLTX
Notes 1, 2
40
40 + 1 x tbit
ms
Trx_on
RX startup time
Powermodes:
STANDBY to FULLRX
190
ms
Trx_rssi
RX startup time to valid RSSI
Powermodes:
STANDBY to FULLRX
Modulation (G)FSK
Notes 1, 2
270 +
3 x tbit
ms
Trx_data
RX startup time to valid data at full
sensitivity/selectivity
190 +
9 x tbit
ms
Trxtx
RX to TX switching
Powermodes:
FULLRX to FULLTX
62
ms
Ttxrx
TX to RX switching
(to preamble start)
Powermodes:
FULLTX to FULLRX
200
Thop
Frequency hop
Switch between frequency de-
fined in register FREQA and
FREQB
30
ms
1. tbit depends on the datarate, e.g. for 10 kbps tbit = 100 ms
2. In wire mode there is a processing delay of typically 6 x tbit between antenna and DCLK/DATA pins



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