AX5043 datasheet(20/47 Pages) ONSEMI

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AX5043

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Registers

Table 19. CHANNEL FILTER AND DEMODULATOR REGISTERS

Remarks

DECIMATION

This register programs the bandwidth of the digital channel filter.

RXDATARATE2… RXDATARATE0

These registers specify the receiver bit rate, relative to the channel filter bandwidth.

MAXDROFFSET2… MAXDROFFSET0

These registers specify the maximum possible data rate offset.

MAXRFOFFSET2… MAXRFOFFSET0

These registers specify the maximum possible RF frequency offset.

TIMEGAIN, DRGAIN

These registers specify the aggressiveness of the receiver bit timing recovery. More

aggressive settings allow the receiver to synchronize with shorter preambles, at the

expense of more timing jitter and thus a higher bit error rate at a given signal−to−noise

ratio.

MODULATION

This register selects the modulation to be used by the transmitter and the receiver,

i.e. whether ASK, FSK should be used.

PHASEGAIN, FREQGAINA, FREQGAINB, FRE-

QGAINC, FREQGAIND, AMPLGAIN

These registers control the bandwidth of the phase, frequency offset and amplitude

tracking loops.

AGCGAIN

This register controls the AGC (automatic gain control) loop slopes, and thus the

speed of gain adjustments. The faster the bit−rate, the faster the AGC loop should be.

TXRATE

These registers control the bit rate of the transmitter.

FSKDEV

These registers control the frequency deviation of the transmitter in FSK mode. The

receiver does not explicitly need to know the frequency deviation, only the channel

filter bandwidth has to be set wide enough for the complete modulation to pass.

Encoder

The encoder is located between the Framing Unit, the

Demodulator and the Modulator. It can optionally transform

the bit−stream in the following ways:

• It can invert the bit stream.

• It can perform differential encoding. This means that a

zero is transmitted as no change in the level, and a one

is transmitted as a change in the level.

• It can perform Manchester encoding. Manchester

encoding ensures that the modulation has no DC

content and enough transitions (changes from 0 to 1 and

from 1 to 0) for the demodulator bit timing recovery to

function correctly, but does so at a doubling of the data

rate.

• It can perform spectral shaping (also know as

whitening). Spectral shaping removes DC content of

the bit stream, ensures transitions for the demodulator

bit timing recovery, and makes sure that the transmitted

spectrum does not have discrete lines even if the

transmitted data is cyclic. It does so without adding

additional bits, i.e. without changing the data rate.

Spectral Shaping uses a self synchronizing feedback

shift register.

The encoder is programmed using the register

ENCODING, details and recommendations on usage are

given in the AX5043 Programming Manual.

Framing and FIFO

Most radio systems today group data into packets. The

framing unit is responsible for converting these packets into

a bit−stream suitable for the modulator, and to extract

packets from the continuous bit−stream arriving from the

demodulator.

The Framing unit supports two different modes:

• Packet modes

• Raw modes

The micro−controller communicates with the framing

unit through a 256 byte FIFO. Data in the FIFO is organized

in Chunks. The chunk header encodes the length and what

data is contained in the payload. Chunks may contain packet

data, but also RSSI, Frequency offset, Timestamps, etc.

The AX5043 contains one FIFO. Its direction is switched

depending on whether transmit or receive mode is selected.

The FIFO can be operated in polled or interrupt driven

modes. In polled mode, the microcontroller must

periodically read the FIFO status register or the FIFO count

In interrupt mode EMPTY, NOT EMPTY, FULL, NOT

FULL and programmable level interrupts are provided. The

AX5043 signals interrupts by asserting (driving high) its

IRQ line. The interrupt line is level triggered, active high.

Interrupts are acknowledged by removing the cause for the

interrupt, i.e. by emptying or filling the FIFO.

Basic FIFO status (EMPTY, FULL, Overrun, Underrun,

FIFO fill level above threshold, FIFO free space above

threshold) are also provided during each SPI access on

MISO while the micro− controller shifts out the register

address on MOSI. See the SPI interface section for details.

This feature significantly reduces the number of SPI

accesses necessary during transmit and receive.

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