AX5043

www.onsemi.com

24

Table 27. SPI STATUS BITS

SPI Bit Cell

Meaning / Register Bit

Status

3

S12

FIFO UNDER

4

S11

THRESHOLD FREE (FIFOFREE > FIFOTHRESH)

5

S10

THRESHOLD COUNT (FIFOCOUNT > FIFOTHRESH)

6

S9

FIFO FULL

7

S8

FIFO EMPTY

8

S7

PWRGOOD (not BROWNOUT)

9

S6

PWR INTERRUPT PENDING

10

S5

RADIO EVENT PENDING

11

S4

XTAL OSCILLATOR RUNNING

12

S3

WAKEUP INTERRUPT PENDING

13

S2

LPOSC INTERRUPT PENDING

14

S1

GPADC INTERRUPT PENDING

15

S0

internal

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

SPI Timing

Figure 6. SPI 8 Bit Read/Write Access with Timing

Tsh

R/ W

SEL

CLK

MOSI

MISO

A6

A5

A4

A3

A2

A1

D7

A0

D6

D5

D4

D0

D1

D2

D3

D7

D6

D5

D4

D3

D2

D1

D0

S14

S13

S12

S11

S10

S9

S8

Tssd

Tco

Tss

Tck TchTcl

Th

Ts

Tssz

Figure 7. SPI 8 Bit Long Address Read/Write Access

R/W

SEL

CLK

MOSI

MISO

A6

A5

A4

A3

A2

A1

D7

A0

D6

D5

D4

D0

D1

D2

D3

D7

D6

D5

D4

D3

D2

D1

D0

S6

S5

S4

S3

S2

S1

S0

A11

A10

A9

A7

A8

S7

S14

S13 S12 S11

S10

S9

S8

Figure 8. SPI 16 Bit Long Read/Write Access

R/W

SEL

CLK

MOSI

MISO

D6

D5

D4

D3

D2

D1

D7

D0

D6

D5

D4

D0

D1

D2

D3

D7

D6

D5

D4

D3

D2

D1

D0

D6

D5

D4

D3

D2

D1

D0

A3

A2

A1

D7

A0

D7

S14 S13 S12 S11

S10

S9

S8

A6

A5

A4

Wire Mode Interface

In wire mode the transmitted or received data are

transferred from and to the AX5043 using the pins DATA

and DCLK. DATA is an input when transmitting and an

output when receiving.

The direction can be chosen by programming the

PWRMODE register.

Wire mode offers two variants: synchronous or

asynchronous.