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AX5043 Datasheet(PDF) 19 Page - ON Semiconductor

Part # AX5043
Description  Advanced High Performance ASK and FSK Narrow-band Transceiver for 27-1050 MHz Range
PDF  47 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

AX5043 Datasheet(HTML) 19 Page - ON Semiconductor

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AX5043
www.onsemi.com
19
Registers
Table 18. RF FREQUENCY GENERATION REGISTERS
Register
Bits
Purpose
PLLLOOP
PLLLOOPBOOST
FLT[1:0]
Synthesizer loop filter bandwidth and selection of external loop filter, recommended usage is to
increase the bandwidth for faster settling time, bandwidth increases of factor 2 and 5 are possi-
ble.
PLLCPI
PLLCPIBOOST
Synthesizer charge pump current, recommended usage is to decrease the bandwidth (and
improve the phase−noise) for low data−rate transmissions.
PLLVCODIV
REFDIV
Sets the synthesizer reference divider ratio.
RFDIV
Sets the synthesizer output divider ratio.
VCOSEL
Selects either the internal or the external VCO
VCO2INT Selects either the internal VCO inductor or an external inductor between pins L1 and L2
FREQA, FREQB
Programming of the carrier frequency
PLLRANGINGA, PLLRANGINGB
Initiate VCO auto−ranging and check results
RF Input and Output Stage (ANTP/ANTN/ANTP1)
The AX5043 has two main antenna interface modes:
1. Both RX and TX use differential pins ANTP and
ANTN. RX/TX switching is handled internally.
This mode is recommended for highest output
powers, highest sensitivities and for direct
connection to dipole antennas. Also see Figure 13.
2. RX uses the differential antenna pins ANTP and
ANTN. TX uses the single ended antenna pin
ANTP1. RX/TX switching is handled externally.
This can be done either with an external RX/TX
switch or with a direct tie configuration. This
mode is recommended for low output powers at
high efficiency (Figure 16) and for usage with
external power amplifiers (Figure 15).
Pin PWRAMP can be used to control an external RX/TX
switch when operating the device together with an external
PA (Figure 15). Pin ANTSEL can be used to control an
external antenna switch when receiving with two antennas
(Figure 17).
When antenna diversity is enabled, the radio controller
will, when not in the middle of receiving a packet,
periodically probe both antennas and select the antenna with
the highest signal strength. The radio controller can be
instructed to periodically write both RSSI values into the
FIFO. Antenna diversity mode is fully automatic.
LNA
The LNA amplifies the differential RF signal from the
antenna and buffers it to drive the I/Q mixer. An external
matching network is used to adapt the antenna impedance to
the IC impedance. A DC feed to GND must be provided at
the antenna pins. For recommendations see section:
Application Information.
PA
In TX mode the PA drives the signal generated by the
frequency generation subsystem out to either the differential
antenna terminals or to the single ended antenna pin. The
antenna terminals are chosen via the bits TXDIFF and TXSE
in register MODECFGA.
The output power of the PA is programmed via the register
TXPWRCOEFFB.
The PA can be digitally pre−distorted for high linearity.
The output amplitude can be shaped (raised cosine), this
mode is selected with bit AMPLSHAPE in register
MODECFGA. PA ramping is programmable in increments
of the bit time and can be set to 1 – 8 bit times via bits
SLOWRAMP in register MODECFGA
.
Output power as well as harmonic content will depend on
the external impedance seen by the PA, recommendations
are given in the section: Application Information.
Digital IF Channel Filter and Demodulator
The digital IF channel filter and the demodulator extract
the data bit−stream from the incoming IF signal. They must
be programmed to match the modulation scheme as well as
the data−rate. Inaccurate programming will lead to loss of
sensitivity.
The channel filter offers bandwidths of 995 Hz up to
221 kHz.
The AXSEM RadioLab Software calculates the necessary
register settings for optimal performance and details can be
found in the AX5043 Programming Manual. An overview
of the registers involved is given in the following table as
reference. The register setups typically must be done once
at power−up of the device.



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