XGS datasheet(11/53 Pages) ONSEMI

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XGS Family

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Figure 8. Typical Configuration (Four−Wire Serial Interface)

VAA

VAA_PIX

VAA_RD

VAA_PIX

_BST

VDD_IO

VDD

VDD_SLVS

VDD_PLL

XGS 12000

XGS 9400

XGS 8000

FWSI_EN

32.4 MHz

EXTCLK

SDATA

SCLK

CS_N

RESET_N

TRIG_INT

TRIG_RD

D_CLK_[2,3]_P

D_CLK_[2,3]_N

DATA_[0:23]_P

DATA_[0:23]_N

MONITOR_0

MONITOR_1

MONITOR_2

SDATAOUT

Digital I/O

(2.8 V)

Digital Core

(1.2 V)

HiSPi

(1.2 V)

PLL

(2.8 V)

Analog

(2.8 V)

Analog (Pixel)

(3.0 V)

RESERVED

100

N.C.

10k

1. All power supplies must be adequately decoupled (see Table 4) Decoupling.

2. In this example, only 2 (out of 6) HiSPi clock lanes are used; D_CLK_2 to sample data on the even data lanes (top readout) and

D_CLK_3 to sample data on the odd data lanes (bottom readout).

3. The active HiSPi lanes need to be terminated using 100 W resistors placed as close to the receiver as possible.

4. Unused HiSPi outputs (data and/or clock lanes) must be left floating.

5. It is highly recommended to route the monitor signals to the receiver (FPGA) for debugging purposes. If the MONITOR outputs

are not used, they must be left floating.

6. If the TRIGGER inputs are not used, tie them to GND.

7. No distinction is made between analog and digital ground (internally shorted).

8. FWSI_EN must be connected to VDD_IO through a 10 kW resistor (enable Four−Wire Serial Interface).

9. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.

10. Digital inputs RESET_N and CS_N are both active low.

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