XGS datasheet(33/53 Pages) ONSEMI

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XGS Family

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Message Byte

Message bytes are used for sending register addresses and

Acknowledge Bit

Each 8−bit data transfer is followed by an acknowledge bit

or a no−acknowledge bit in the SCLK clock period following

the data transfer. The transmitter (which is the master when

writing, or the slave when reading) releases SDATA. The

receiver indicates an acknowledge bit by driving SDATALOW.

As for data transfers, SDATA can change when SCLK is LOW

and must be stable while SCLK is HIGH.

No−Acknowledge Bit

The no−acknowledge bit is generated when the receiver

does not drive SDATA LOW during the SCLK clock period

following a data transfer. A no−acknowledge bit is used to

terminate a read sequence.

Typical Sequence

A typical READ or WRITE sequence begins by the

master generating a start condition on the bus. After the start

condition, the master sends the 8−bit slave address/data

direction byte. The last bit indicates whether the request is

for a read or a write, where a ’0’ indicates a write and a ’1’

indicates a read. If the address matches the address of the

slave device, the slave device acknowledges receipt of the

address by generating an acknowledge bit on the bus.

If the request was a WRITE, the master then transfers the

16−bit register address to which the WRITE should take

place. This transfer takes place as two 8−bit sequences and

the slave sends an acknowledge bit after each sequence to

indicate that the byte has been received. The master then

transfers the data as an 8−bit sequence; the slave sends an

acknowledge bit at the end of the sequence. The master stops

writing by generating a (re)start or stop condition.

If the request was a READ, the master sends the 8−bit

write slave address/data direction byte and 16−bit register

address, the same way as with a WRITE request. The master

then generates a (re)start condition and the 8−bit read slave

address/data direction byte, and clocks out the register data,

eight bits at a time. The master generates an acknowledge bit

after each 8−bit transfer. The slave

’s internal register address

is automatically incremented after every 8 bits are

transferred. The data transfer is stopped when the master

sends a no−acknowledge bit.

Single READ from Random Location

This sequence (Figure 39) starts with a dummy WRITE to

the 16−bit address that is to be used for the READ. The

master terminates the WRITE by generating a restart

condition. The master then sends the 8−bit read slave

address/data direction byte and clocks out one byte of

generating a no−acknowledge bit followed by a stop

condition. Figure 39 shows how the internal register address

maintained by the sensor is loaded and incremented as the

sequence proceeds.

Previous Reg Address, N

Reg Address, M

M+1

Slave Ad−

dress

Reg

Address[15:8]

Reg

Address[7:0]

Slave Address

S = Start Condition

P = Stop Condition

Sr = Restart Condition

A = Acknowledge

A = No−acknowledge

Slave to Master

Master to Slave

Read Data

Figure 39. Single READ from Random Location

Single READ from Current Location

This sequence (Figure 40) performs a read using the

current value of the sensor’s internal register address. The

master terminates the READ by generating a

no−acknowledge bit followed by a stop condition. The

figure shows two independent READ sequences.

Previous Reg Address, N

Reg Address, N+1

N+2

Slave Address

Read Data

Slave Address

Read Data

Figure 40. Single READ from Current Location

XGS Datasheet(PDF) 33 Page - ON Semiconductor

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