XGS datasheet(14/53 Pages) ONSEMI

14 / 53 page

XGS Family

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PIN LIST

Table 5. PIN DESCRIPTIONS (163−PIN LGA PACKAGE)

Name

LGA Pin Name

Type

Description

GND

A1, A18, C3, C7, C12, C16, F4, F15,

G3, G16, J4, J15, K3, K16, M4, M11,

M15, N8, N11, P7, P12, T3, T10, T16,

V1, V18, D12, F10, G8, G9, G10, G11,

P6, P13

Ground

VDD_PLL

C10

Power

PLL Power Supply

VAA

C5, C14, M9, M10, N3, N9, N10, N16,

R5, R6, R13, R14, T9

Power

Analog Supply

VAA_RD

C6, C13, T5, T14

Power

Analog Supply for Row Driver

VDD_IO

C8, C9, C11, P3, P16

Power

I/O Supply

FWSI_EN

D10

Input

’HIGH’ −> Four−Wire Serial Interface (SPI)

’LOW’ −> Two−Wire Serial Interface (I2C)

SDATA

D11

Input/

Output

Four−Wire Serial Interface (SPI): SPI Slave In

Two−Wire Serial Interface (I2C): Serial Data Input/

Output

VAA_PIX

D5, D14, P5, P14

Power

Pixel Supply

VDD

D6, D13, E3, E16, F7, F12, H3, H16,

J7, J12, L3, L16, M7, M12

Power

Digital Supply

MONITOR_2

Output

Monitor Output 2. If unused, do not connect.

MONITOR_1

Output

Monitor Output 1. If unused, do not connect.

EXTCLK

Input

External Clock Input

SDATAOUT

E10

Output

Four−Wire Serial Interface (SPI): SPI Slave Out

Two−Wire Serial Interface (I2C): Do not connect

TRIG_RD

E11

Input

Trigger Input for Readout Control. If unused, connect to

ground.

DATA_0_N

E12

HiSPi

Differential Data Channel [0], Negative

DATA_0_P

E13

HiSPi

Differential Data Channel [0], Positive

DATA_2_N

E14

HiSPi

Differential Data Channel [2], Negative

DATA_2_P

E15

HiSPi

Differential Data Channel [2], Positive

DATA_3_P

HiSPi

Differential Data Channel [3], Positive

DATA_3_N

HiSPi

Differential Data Channel [3], Negative

DATA_1_P

HiSPi

Differential Data Channel [1], Positive

DATA_1_N

HiSPi

Differential Data Channel [1], Negative

MONITOR_0

Output

Monitor Output 0. If unused do not connect.

CS_N

Input

Four−Wire Serial Interface (SPI): SPI Chip Select (active low)

Two−Wire Serial Interface (I2C): Connect to GND

TRIG_INT

F11

Input

Trigger Input for Integration Control. If unused, connect to

ground.

D_CLK_0_N

F13

HiSPi

Differential Clock [0], Negative

D_CLK_0_P

F14

HiSPi

Differential Clock [0], Positive

VDD_SLVS

F3, F16, J3, J16, M3, M16

Power

HiSPi Supply

D_CLK_1_P

HiSPi

Differential Clock [1], Positive

D_CLK_1_N

HiSPi

Differential Clock [1], Negative

RESET_N

Input

Asynchronous Hard Reset (Active Low)

SCLK

Input

Serial Interface Clock Input

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