XGS datasheet(32/53 Pages) ONSEMI

32 / 53 page

XGS Family

www.onsemi.com

SENSOR CONTROL INTERFACE

The sensor’s configuration registers are accessible

through either the Two−Wire (I2C) or Four−Wire (SPI)

Serial Interface. At the cost of speed, the two−wire serial

interface can be considered as a simple and cost−efficient

alternative to the faster, but more complex, four−wire serial

interface. The four−wire serial interface is recommended for

applications

requiring

fast

and

frequent

sensor

(re−)configuration. As shown in Figure 38 below, the type

of user interface can be selected through the external

FWSI_EN pin (‘LOW’ = two−wire, ‘HIGH’ = four−wire).

FWSI_EN

SDATA(I/O)

SCLK

CS_N

SDATAOUT

N.C.

VDD_IO

Two-Wire

FWSI_EN

SDATA

SCLK

CS_N

SDATAOUT

Four-Wire

VDD_IO

Figure 38. Serial Interface Selection

TWO−WIRE SERIAL INTERFACE

The two−wire serial interface bus enables read/write

access to control and status registers within the sensor.

The interface protocol uses a master/slave model in which

a master controls one or more slave devices. The sensor acts

as a slave device. The master generates a clock (SCLK) that

is an input to the sensor and is used to synchronize transfers.

Data is transferred between the master and the slave on a

bidirectional signal (SDATA). SDATA is pulled up to VDD_IO

off−chip by a 1.5 k

W resistor. Either the slave or master

device can drive SDATA LOW − the interface protocol

determines which device is allowed to drive SDATA at any

given time.

The protocols described in the two−wire serial interface

specification allow the slave device to drive SCLK LOW; the

sensor uses SCLKas an input only and therefore never drives

it LOW.

Protocol

Data transfers on the two−wire serial interface bus are

performed by a sequence of low−level protocol elements:

• a (repeated) start condition

• a slave address/data direction byte

• an (a no) acknowledge bit

• a message byte

• a stop condition

The bus is idle when both SCLK and SDATA are HIGH.

Control of the bus is initiated with a start condition, and the

bus is released with a stop condition. Only the master can

generate the start and stop conditions.

Start Condition

A start condition is defined as a HIGH−to−LOW

transition on SDATA while SCLK is HIGH. At the end of a

transfer, the master can generate a start condition without

previously generating a stop condition; this is known as a

”repeated start” or ”restart” condition.

Stop Condition

A stop condition is defined as a LOW−to−HIGH transition

on SDATA while SCLK is HIGH.

Data Transfer

Data is transferred serially, 8 bits at a time, with the MSB

transmitted first. Each byte of data is followed by an

acknowledge bit or a no−acknowledge bit. This data transfer

mechanism is used for the slave address/data direction byte

and for message bytes.

One data bit is transferred during each SCLK clock period.

SDATA can change when SCLK is LOW and must be stable

while SCLK is HIGH.

Slave Address/Data Direction Byte

Bits [7:1] of this byte represent the device slave address

and bit [0] indicates the data transfer direction. A ’0’ in bit

[0] indicates a WRITE, and a ’1’ indicates a READ.

The default slave addresses used by the sensor are 0x20

(write address) and 0x21 (read address).

XGS Datasheet(PDF) 32 Page - ON Semiconductor

XGS Datasheet(HTML) 32 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL