XGS datasheet(37/53 Pages) ONSEMI

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XGS Family

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ELECTRICAL SPECIFICATIONS

Unless stated otherwise, the following specifications

apply to the following conditions:

VAA_PIX = VAA_PIX_BST = VAA_RD = 3.0 V;

VAA = VDD_PLL = 2.8 V;

VDD_IO = 1.8 V;

VDD = 1.2 V;

VDD_SLVS = 1.2 V;

EXTCLK = 32.4 MHz;

TA = 25°C;

TWO−WIRE SERIAL REGISTER INTERFACE

The electrical characteristics of the two−wire serial

Table 13.

SDATA

SCLK

tSU;DAT

tHD;STA

tSU;STO

tSU;STA

tBUF

tHD;DAT

tHIGH

tLOW

tHD;STA

NOTE: Read sequence: For an 8−bit READ, read waveforms start after WRITE command and register address are issued.

Figure 49. Two−Wire Serial Bus Timing Parameters

Table 13. TWO−WIRE SERIAL BUS CHARACTERISTICS

Parameter

Symbol

Standard Mode

Fast−Mode

Unit

Min

Max

Min

Max

SCLK Clock Frequency

fSCL

100

400

kHz

Hold Time (Repeated) START Condition

tHD;STA

4.0

0.6

LOW Period of the SCLK Clock

tLOW

4.7

1.3

HIGH Period of the SCLK Clock

tHIGH

4.0

0.6

Set−up Time for a Repeated START Condition

tSU;STA

4.7

0.6

Data Hold Time

tHD;DAT

0 (Note 11)

3.45

(Note 12)

0 (Note 13)

0.9

(Note 12)

Data Set−up Time

tSU;DAT

250

100

(Note 13)

Rise Time of both SDATA and SCLK Signals

1000

20 + 0.1Cb

(Note 14)

300

Fall Time of both SDATA and SCLK Signals

300

20 + 0.1Cb

(Note 14)

300

Set−up Time for STOP Condition

tSU;STO

4.0

0.6

Bus Free Time between a STOP and START Condition

tBUF

4.7

1.3

Capacitive Load for each Bus Line

400

Serial Interface Input Pin Capacitance

CIN_SI

3.3

SDATA Max Load Capacitance

CLOAD_SD

SDATA Pull−up Resistor

RSD

1.5

4.7

1.5

4.7

9. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.

10.Two−wire control is I2C−compatible.

11. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.

12.The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.

13.A Fast−mode I2C−bus device can be used in a Standard−mode I2C−bus system, but the requirement tSU;DAT 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW

period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard

mode I2C−bus specification) before the SCLK line is released.

14.Cb = total capacitance of one bus line in pF.

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