6 Pin Configuration and Functions

VP

AGND

SW

VOUT

PGND

BOOT

VIN

EN/UVLO

ISEL

ILIM

COMP

FB

1

VCC

2

3

4

5

6

7

8

9

10

11

12

13

Figure 6-1. 13-Pin RYH VQFN Package (Top View)

Table 6-1. Pin Functions

PIN

I/O

DESCRIPTION

NAME

NUMBER

VIN

1

I

IC power supply input

EN/UVLO

2

I

Enable logic input and programmable input voltage undervoltage lockout (UVLO) input.

Logic high level enables the device. Logic low level disables the device and turns it

into shutdown mode. The converter start-up and shutdown levels can be programmed by

connecting this pin to the supply voltage through a resistor divider.

ISEL

3

I

Scale the ISO FET to improve input average current limit accuracy and adjust peak

switching current limit value.

ISEL = low when setting Ilimit ≤ 750 mA

ISEL = high, when setting Ilimit > 750 mA

VOUT

4

PWR

Boost converter output

VP

5

PWR

Drain of the ISO MOSFET

SW

6

PWR

The switching node pin. It is connected to the drain of the internal low-side power MOSFET

and the source of the internal ISO power MOSFET.

PGND

7

PWR

Power ground of the IC

FB

8

I

Output voltage feedback pin. Connect to the center tape of a resistor divider to program the

output voltage.

COMP

9

O

Output of the internal error amplifier. Connect the loop compensation network between this

pin and the AGND pin.

ILIM

10

I

Input average current limit setting pin. Use a resistor between this pin and AGND to set the

desired input average current limit threshold.

VCC

11

O

Output of the internal regulator. A ceramic capacitor of more than 1 μF is required between

this pin and AGND.

AGND

12

PWR

Analog ground of the IC

BOOT

13

O

Power supply for ISO MOSFET gate driver. A ceramic capacitor of more than 0.47 μF must

be connected between this pin and the SW pin.

TPS61376

SLVSGQ1A – JANUARY 2022 – REVISED SEPTEMBER 2022

www.ti.com

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