CS47L85 datasheet(365/370 Pages) CIRRUS

Part #	CS47L85

Description	Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub

PDF	370 Pages

Scroll/Zoom	100%

Manufacturer	CIRRUS [Cirrus Logic]

Direct Link	http://www.cirrus.com

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365 / 370 page

CS47L85

Rev 4.3

365

In each case, the SYSCLK (ASYNCCLK) frequency must be a valid ratio to the LRCLK frequency; the supported clocking

rates are defined by the SYSCLK_FREQ (ASYNC_CLK_FREQ) and SAMPLE_RATE_n (ASYNC_SAMPLE_RATE_n)

registers.

The valid AIF clocking configurations are illustrated in Figure 99 to Figure 105 below. Note that, where MCLK1 is illustrated

as the clock source, it is equally possible to select MCLK2 as the clock source. Similarly, in cases where FLL1 is illustrated,

it is equally possible to select FLL2 or FLL3.

AIFn

(Master Mode)

Oscillator

CS47L85

Processor

AIFnBCLK

AIFnLRCLK

AIFnRXDAT

AIFnTXDAT

SYSCLK

(or ASYNCCLK)

SYSCLK_SRC

(or ASYNCCLK_SRC)

Figure 99 AIF Master Mode, using MCLK as Reference

Oscillator

CS47L85

AIFn

(Master Mode)

Processor

AIFnBCLK

AIFnLRCLK

AIFnRXDAT

AIFnTXDAT

FLL1_REFCLK_SRC

FLL1

SYSCLK

(or ASYNCCLK)

SYSCLK_SRC

(or ASYNCCLK_SRC)

Figure 100 AIF Master Mode, using MCLK and FLL as Reference

CS47L85 Datasheet(PDF) 365 Page - Cirrus Logic