CS47L85 datasheet(369/370 Pages) CIRRUS

369 / 370 page

CS47L85

Rev 4.3

369

Revision History

Table 141 Revision History

Revision

Changes

1.0

SEP ‘14

• Initial version

1.1

DEC ‘14

• Thermal Characteristics added

• Correction to PWMn_LVL description

• Updates to DSP Clocking registers and controls

• Added description of DSP DMA functions

• Changes to Master Interface registers and operation

• Updates to Timer Clocking registers and controls

• Updates to SLIMbus register access description

• Output Path Hi-Fi filter controls added

• Recommended 500k JACKDET2 resistor connection

1.1

JAN ‘15

• SPI clock frequency spec updated

• Recommend TRST is tied to DGND if JTAG function is not used

• Noted SYSCLK_ENA and ASYNC_CLK_ENA must be set to 0 before the respective clock source is stopped

• Noted 32kHz clock requirement for GPIO input de-bounce

• Clocking required for FLL Interrupt

• DSP_CLK_FREQ_RANGE defined (replaces DSP_CLK_FREQ)

• CIF1MISO pull-down described

• Signal Timing Requirements updated

• DSP memory reset behaviour corrected

• Electrical Characteristics updated

• GPIO functions updated (added/removed)

• Sleep Mode requirements (external DCVDD) added

2.0

MAY

‘15

• Converted to Cirrus document template

• Sleep Mode requirements (external DCVDD) deleted

• DBVDD operating range updated

• Signal passband noted for each DMIC clock frequency

• Clarification of voltage domains for DMIC operation

• Register Map listing is referenced to a separate document

• CPVDD2 absolute maximum rating updated

• Noted DCVDD/FLLVDD must be tied together

• Digital Mixer control requirements updated

4.0

MAY ‘15

•

Updated to ‘Production Data’ status

4.1

JUL ‘15

• Clarification of SLIMbus requirements for different Transport Protocol (TP) options

• FLL1_DIV6 system clocking option added

• Correction to FLL Spread Spectrum control register (FLLn_SS_SEL) description

• Noted constraints for using WSEQ_START to trigger the Control Sequencer

• System clocking control requirements updated

• Added comments describing bus-keeper start-up condition, and digital I/O in Sleep Mode

4.2

DEC

‘16

• Series resistor recommended on FLLVDD connection

• Clarification of PDM input/output digital signal levels

• Typical performance data added

• DSPn_DMA_WORD_SEL description added

• Master interface section updated to include clocking requirements

• Output path noise gate threshold (NGATE_THR) updated

• Headphone detect (HPDET) calculation and measurement time updated

• FLL configuration and example settings updated

4.3

APR ‘18

• ANC amended to mono function only

CS47L85 Datasheet(PDF) 369 Page - Cirrus Logic

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