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VS1103b Datasheet

SPI BUSES

5.4.3

SDI in VS1001 Compatibility Mode

BSYNC

SDATA

DCLK

Figure 3: BSYNC Signal - one byte transfer.

When VS1103b is running in VS1001 compatibility mode, a BSYNC signal must be generated

to ensure correct bit-alignment of the input bitstream. The ﬁrst DCLK sampling edge (rising or

falling, depending on selected polarity), during which the BSYNC is high, marks the ﬁrst bit of

a byte (LSB, if LSB-ﬁrst order is used, MSB, if MSB-ﬁrst order is used). If BSYNC is ’1’ when

the last bit is received, the receiver stays active and next 8 bits are also received.

BSYNC

SDATA

DCLK

Figure 4: BSYNC Signal - two byte transfer.

5.4.4

Passive SDI Mode

If SM_NEWMODE is 0 and SM_SDISHARE is 1, the operation is otherwise like the VS1001

compatibility mode, but bits are only received while the BSYNC signal is ’1’. Rising edge of

BSYNC is still used for synchronization.

5.5

Serial Protocol for Serial Command Interface (SCI)

5.5.1

General

The serial bus protocol for the Serial Command Interface SCI (Chapter 6.5) consists of an

instruction byte, address byte and one 16-bit data word. Each read or write operation can read

or write a single register. Data bits are read at the rising edge, so the user should update data

at the falling edge. Bytes are always sent MSb ﬁrst. XCS should be low for the full duration of

the operation, but you can have pauses between bits if needed.

The operation is speciﬁed by an 8-bit instruction opcode. The supported instructions are read

and write. See table below.

Instruction

Name

Opcode

Operation

READ

0b0000 0011

Read data

WRITE

0b0000 0010

Write data

Note: VS1103b sets DREQ low after each SCI operation. The duration depends on the opera-

tion. It is not allowed to ﬁnish a new SCI/SDI operation before DREQ is high again.

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